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CN-114730750-B - Three-dimensional stacked integrated circuit using immersion cooling method based on semiconductor package and open-pore interposer

CN114730750BCN 114730750 BCN114730750 BCN 114730750BCN-114730750-B

Abstract

A package having a semiconductor chip and an interposer substrate having an opening are alternately stacked via respective electrode terminals and electrode pads, the package and the interposer substrate having electrode terminals and electrode pads in a shape that a gap is formed between the electrode terminals and the package in a stacked state, and guide holes for connecting the electrode terminals, and for maintaining accurate positioning and connection at the time of stacking, an interlayer communication path is formed by connecting the package and the interposer substrate, and immersion cooling is performed by flowing a cooling liquid in the gap.

Inventors

  • TSUTSUI TAKASHI

Assignees

  • 软银股份有限公司

Dates

Publication Date
20260505
Application Date
20201125
Priority Date
20191205

Claims (11)

  1. 1. A three-dimensional stacked integrated circuit is provided with a package having a semiconductor chip and an interposer substrate having an opening at a position where the semiconductor chip is mounted, the interposer substrate being alternately stacked by respective electrode terminals and electrode pads, The package and the interposer substrate are in a shape such that a gap is generated between the electrode terminals and the package in a stacking direction by the electrode terminals on the lower surface, Electrode pads of geometric shapes for connecting the electrode terminals are arranged on the upper surfaces of the packaging piece and the medium layer substrate, The electrode terminals and the electrode pads of the package and the interposer substrate are electrically connected in 1:1 up and down, Guide holes for accurately positioning and holding connection at the time of lamination are provided in the package and the interposer substrate, An interlayer communication path is formed by the electrode terminal and the electrode pad through the connection of the package and the interposer substrate, The immersion cooling is performed by flowing a cooling liquid in a gap created between the package and the electrode terminals of the interposer substrate.
  2. 2. The three-dimensional stacked integrated circuit of claim 1, wherein, The interposer substrate interposed between the packages is continuously interposed with a plurality of pieces.
  3. 3. The three-dimensional stacked integrated circuit of claim 1, wherein, The semiconductor chip mounted in the package is a laminated three-dimensional semiconductor of two or more layers (HBM, high Bandwidth Memory, i.e., high bandwidth memory, wide I/O DRAM, etc.).
  4. 4. The three-dimensional stacked integrated circuit according to any one of claim 1 to 3, wherein, The packages are of a NUMA (Non-Uniform Memory Access ) structure formed by cross connection, and the interconnection of the packages becomes bus connection.
  5. 5. The three-dimensional stacked integrated circuit according to any one of claim 1 to 3, wherein, The guide holes have both functions as electrodes for supplying power to the anode and the cathode of the semiconductor chip mounted on the package, and two adjacent guide holes are provided so as to reduce impedance and directly supply power to the ceramic capacitor mounted on the package.
  6. 6. The three-dimensional stacked integrated circuit according to any one of claim 1 to 3, wherein, The data transmission system of the interlayer communication path formed by the electrode terminals and the electrode pads is set to LVD (Low Voltage Differential, i.e., low-voltage differential) with the pair of the adjacent two electrode terminals.
  7. 7. The three-dimensional stacked integrated circuit according to any one of claim 1 to 3, wherein, The data transmission system of the interlayer communication path formed by the electrode terminals and the electrode pads is PCI Express, with the pair of the two adjacent electrode terminals.
  8. 8. The three-dimensional stacked integrated circuit of claim 7, wherein, Use PCI Express after adding frequency.
  9. 9. The three-dimensional stacked integrated circuit according to any one of claim 1 to 3, wherein, In order to reduce the adverse effect of reflection of a high-frequency signal flowing through the interlayer communication path, a bidirectional tri-state gate driver is mounted adjacent to the electrode terminal of the package.
  10. 10. The three-dimensional stacked integrated circuit according to any one of claim 1 to 3, wherein, In order to prevent cavitation due to intermittent boiling during immersion cooling, the heat sink in close contact with the semiconductor chip mounted on the package is a sintered metal or an oxidized metal.
  11. 11. The three-dimensional stacked integrated circuit according to any one of claim 1 to 3, wherein, The lowermost integrated circuit of the three-dimensional stacked integrated circuit is constituted by a bus driver switch or a bus driver buffer switch with address bus snooping and DMA with buffer in units of pages.

Description

Three-dimensional stacked integrated circuit using immersion cooling method based on semiconductor package and open-pore interposer Technical Field The present invention relates to a three-dimensional stacked integrated circuit having a cooling function based on a refrigerant, and a method for cooling the three-dimensional stacked integrated circuit. Background There is a mounting technology of three-dimensionally stacked semiconductors. For example, the applicant has disclosed a three-dimensional stacked integrated circuit including interposer layers respectively provided between integrated circuits of the three-dimensional stacked integrated circuit and under the lowermost integrated circuit, wherein a plurality of the interposer layers are provided with a path for moving a refrigerant, and a plurality of the refrigerant paths provided in the plurality of interposer layers are connected to each other (see patent document 1). Prior art literature Patent literature Patent document 1 International publication No. 2019/146724 Disclosure of Invention Technical problem to be solved by the invention In the prior art, the heat sink cannot function effectively even if it is interposed between the stacked semiconductors. The heat dissipation caused by the metal plate extending laterally leads to excessive thermal resistance. Although metal, the thermal resistance (ψjt) is proportional to the heat conduction distance of the metal, tj=ψjt×p+tcl (Tj is junction temperature, ψjt is thermal resistance, P is power consumption, and Td is ambient temperature), and power consumption is not applied when ψjt becomes large. Fig. 15 is a cross-sectional view showing how heat propagates after a heat radiating plate is provided on a heat-generating semiconductor chip. The entire semiconductor chip is a heat generating body, but a heat generating portion is a point heat source of the heat generating point A, B, C for the purpose of explaining a heat transfer manner to the heat radiating plate. The heat is diffused from the point heat source in a hemispherical shape (indicated by a semicircle because fig. 15 is a cross-sectional view) with respect to the heat radiation plate. Heat propagates concentrically from the central heat generation point B, but since there is heat from the heat generation point a or the heat generation point B located on the left and right, the heat resistance is large in the left and right direction and hardly propagates. On the other hand, since the thermal resistance in the upward direction is low, the heat sink B and the heat sinks around it effectively function. On the other hand, at the heat generation point a, the heat resistance in the right direction is large due to the heat from the heat generation point B in the center, and therefore the heat propagates upward and leftward. Similarly, at the heat generation point C, the heat resistance in the left direction is large due to the heat from the heat generation point B in the center, and therefore the heat propagates upward and rightward. The heat radiation plate emits heat to the outside with a larger surface area than the heat generating body, and thus is sufficiently larger than the semiconductor chip. Therefore, there is no heat source on the left side of the heat generation point a and the right side of the heat generation point C, and the thermal resistance is small, so that sufficient heat dissipation can be performed by heat dissipation through the surface area of the heat dissipation plate itself, and there is a possibility that the fins of the outer edge portion of the fin a, the fin C, or the like do not function effectively. In order to maximize the effectiveness of the heat sink located directly above the semiconductor chip as the heat generating element, as in the heat sink B, the heat generating spot may be brought close to the heat sink by reducing the thickness of the heat sink as in fig. 16. Therefore, even if the heat dissipation plate is thick or thin, the effectiveness of the heat dissipation plate is questionable when the semiconductor chip is immersed in three dimensions without being accommodated in a BGA package or the like. In an efficient method for impregnating a semiconductor substrate (a portion cut to be as thin as possible on the opposite side of a circuit mounting portion of the semiconductor) without mounting a heat sink, or for impregnating the semiconductor substrate with a relatively thin package metal having a good thermal conductivity, w=j/s, in which case the three-dimensional semiconductor substrate is impregnated on the premise of being based on an FC-BGA package having electrode pads on the surface (three-dimensional mounting of a high heat generating arithmetic circuit such as a CPU and a GPU), the semiconductor substrate (the portion cut to be as thin as possible on the opposite side of the circuit mounting portion of the semiconductor) is directly impregnated (in this case, the FC portion is sealed with an