Search

CN-114758985-B - Semiconductor structure, preparation method thereof and preparation method of transistor device

CN114758985BCN 114758985 BCN114758985 BCN 114758985BCN-114758985-B

Abstract

The invention provides a semiconductor structure, a preparation method thereof and a preparation method of a transistor device. By forming the tensile stress material layer in the window, the diffusion trend of the metal in the metal layer in the substrate is limited to the right lower part of the window to the greatest extent under the action of the tensile stress material layer, the lateral diffusion range of the metal is reduced, and the metal is prevented from diffusing to the peripheral components. For example, in the process of manufacturing a transistor device, the problem that metal in a metal silicide layer in a source-drain region is laterally diffused to a gate structure can be avoided, and the device performance of a formed semiconductor structure is improved.

Inventors

  • LUO QIREN
  • TONG YUCHENG

Assignees

  • 福建省晋华集成电路有限公司

Dates

Publication Date
20260508
Application Date
20220429

Claims (13)

  1. 1. A method of fabricating a semiconductor structure, comprising: Providing a substrate, and forming a dielectric layer on the substrate, wherein a window is formed in the dielectric layer, and the window exposes the substrate; Forming a metal layer, wherein the metal layer at least covers the substrate exposed in the window; Filling a layer of tensile stress material in the fenestration, and An annealing process is performed to react the metal in the metal layer with the silicon in the substrate to form a metal silicide layer in the substrate, the side boundary of the metal silicide layer not exceeding the side boundary of the window.
  2. 2. The method of manufacturing a semiconductor structure of claim 1, wherein the thickness of the metal silicide layer decreases sequentially from a center of the opening to an edge of the opening.
  3. 3. The method of manufacturing a semiconductor structure according to claim 2, wherein a cross-sectional shape of the metal silicide layer in a thickness direction is triangular.
  4. 4. The method of manufacturing a semiconductor structure of claim 1, wherein the material of the tensile material layer comprises silicon nitride.
  5. 5. The method of manufacturing a semiconductor structure of claim 1, wherein a doped region is further formed in the substrate, wherein a window in the dielectric layer exposes the doped region, and wherein the metal silicide layer is formed on the doped region.
  6. 6. The method of manufacturing a semiconductor structure of claim 1, wherein the metal layer is nitrided prior to forming the layer of tensile stress material.
  7. 7. The method of claim 1, wherein forming a metal nitride layer on the metal layer is performed prior to forming the tensile stress material layer.
  8. 8. The method of manufacturing a semiconductor structure according to any one of claims 1-7, further comprising, after performing the annealing process: And sequentially removing the tensile stress material layer and the metal layer which does not react with the substrate, and forming a conductive plug in the window.
  9. 9. A method of manufacturing a transistor device, comprising: Forming a gate structure on a substrate; forming source and drain regions in the substrate beside the gate structure, and A method of fabricating a semiconductor structure as claimed in any one of claims 1 to 8, performed to form a metal silicide layer on the source drain region.
  10. 10. A semiconductor structure, comprising: The dielectric layer is formed on a substrate, and a window is formed in the dielectric layer; A metal layer covering the substrate exposed in the window; A metal silicide layer formed on the substrate exposed in the window, and a side boundary of the metal silicide layer does not exceed a side boundary of the window; And pulling the stress material layer to be in direct contact with the upper surface of the metal layer far away from the metal silicide layer.
  11. 11. The semiconductor structure of claim 10, wherein a thickness of the metal silicide layer decreases sequentially from a center of the opening to an edge of the opening.
  12. 12. The semiconductor structure of claim 11, wherein the metal silicide layer has a triangular cross-sectional shape in a vertical direction.
  13. 13. The semiconductor structure of claim 10, further comprising a metal nitride layer over the metal silicide layer and a conductive plug over the metal nitride layer.

Description

Semiconductor structure, preparation method thereof and preparation method of transistor device Technical Field The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor structure, a method for forming the same, and a method for manufacturing a transistor device. Background In the field of semiconductor technology, metal silicide layers are widely used in a variety of semiconductor devices, for example, metal silicide is commonly used in transistor devices to reduce contact resistance between source and drain regions and conductive plugs. Currently, metal silicide layers are typically formed by reacting a metal with silicon. With the development of semiconductor technology, semiconductor integrated circuits tend to have higher integration, so that the metal silicide layer is easy to diffuse during and after the preparation process of the metal silicide layer, and the metal is easy to diffuse to affect other components. Disclosure of Invention The present invention is directed to a semiconductor structure for solving the problem that metal in a metal silicide layer is easily diffused to peripheral components. The invention provides a preparation method of a semiconductor structure, which comprises the steps of providing a substrate, forming a dielectric layer on the substrate, forming a window in the dielectric layer, exposing the substrate through the window, forming a metal layer at least covering the substrate exposed in the window, filling a tensile stress material layer in the window, and performing an annealing process to enable metal in the metal layer and silicon in the substrate to react to form a metal silicide layer in the substrate. Optionally, a side boundary of the metal silicide layer does not exceed a side boundary of the window. Optionally, the thickness of the metal silicide layer decreases from the center of the window to the edge of the window. Alternatively, the cross-sectional shape of the metal silicide layer in the thickness direction is triangular. Optionally, the material of the tensile stress material layer includes silicon nitride. Optionally, a doped region is further formed in the substrate, and a window in the dielectric layer exposes the doped region, and the metal silicide layer is formed on the doped region. Optionally, nitriding the metal layer prior to forming the tensile stress material layer. Optionally, a metal nitride layer is formed over the metal layer prior to forming the tensile stress material layer. Optionally, after the annealing process is performed, the method further comprises sequentially removing the tensile stress material layer and the metal layer which is not reacted with the substrate, and forming a conductive plug in the window. The invention also provides a preparation method of the transistor device, which comprises the steps of forming a gate structure on a substrate, forming a source-drain region in the substrate at the side edge of the gate structure, and executing the preparation method of the semiconductor structure to form a metal silicide layer on the source-drain region. The invention also provides a semiconductor structure, which comprises a dielectric layer formed on a substrate, wherein a window is formed in the dielectric layer, and a metal silicide layer formed on the substrate exposed in the window, wherein the side boundary of the metal silicide layer does not exceed the side boundary of the window. Optionally, the thickness of the metal silicide layer decreases from the center of the window to the edge of the window. Optionally, the cross section of the metal silicide layer in the vertical direction is triangular. Optionally, the semiconductor structure further comprises a metal nitride layer and a conductive plug, wherein the metal nitride layer is positioned on the metal silicide layer, and the conductive plug is positioned on the metal nitride layer. According to the semiconductor structure and the preparation method thereof, the tensile stress material layer is formed in the window, so that the diffusion trend of metal in the metal layer in the substrate is limited to be right below the window to a greater extent under the action of the tensile stress material layer on the substrate, the lateral diffusion range of the metal is reduced, and further the influence of the diffused metal on peripheral components is avoided. For example, in the process of manufacturing a transistor device, the problem that metal in a metal silicide layer in a source-drain region is laterally diffused to a gate structure can be avoided, and the device performance of a formed semiconductor structure is improved. And, for the formed semiconductor structure, the metal silicide layer is limited in the windowed area and does not extend to the area outside the windowed area, so that adverse effects caused by the diffusion of metal in the metal silicide layer to peripheral components are avoided. Drawings Fig. 1 is a