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CN-114759094-B - Semiconductor structure and preparation method thereof

CN114759094BCN 114759094 BCN114759094 BCN 114759094BCN-114759094-B

Abstract

The embodiment of the disclosure relates to the field of semiconductors, and provides a semiconductor structure and a preparation method thereof, wherein the semiconductor structure comprises a substrate, a first electrode and a second electrode, wherein the substrate comprises an active region; the semiconductor device comprises an active region, a channel layer, a gate structure, a barrier layer and a barrier layer, wherein the channel layer is positioned on the surface of a substrate of the active region, the gate structure is positioned on the surface of the channel layer, the barrier layer is positioned on the surface of the substrate of the active region, the side surface of the barrier layer is in contact with the side surface of the channel layer, and the lattice constant of a material of the channel layer is larger than that of the barrier layer and that of a material of the substrate. The semiconductor structure provided by the embodiment of the disclosure can at least prevent the stress relaxation phenomenon of the channel layer.

Inventors

  • LI DEBIN

Assignees

  • 长鑫存储技术有限公司

Dates

Publication Date
20260512
Application Date
20220427

Claims (14)

  1. 1. A semiconductor structure, comprising: a substrate comprising an active region; the channel layer is positioned on the substrate surface of the active region; a gate structure located on the channel layer surface; the blocking layer is positioned on the surface of the substrate of the active region, the side face of the blocking layer is in contact with the side face of the channel layer, and the lattice constant of the material of the channel layer is larger than that of the blocking layer and the material of the substrate; The top surface of the barrier layer, which is far away from the substrate, is higher than the top surface of the channel layer, which is far away from the substrate, wherein the height difference between the top surface of the barrier layer and the top surface of the channel layer is 10A-100A; The bottom surface of the barrier layer is lower than the bottom surface of the channel layer, and the height difference between the bottom surface of the barrier layer and the bottom surface of the channel layer is 3-5 nm.
  2. 2. The semiconductor structure of claim 1, wherein a lattice constant of a material of the barrier layer is less than or equal to a lattice constant of a material of the substrate of the active region.
  3. 3. The semiconductor structure of claim 1, wherein the barrier layer comprises an epitaxial semiconductor layer.
  4. 4. The semiconductor structure of claim 3, wherein a material of the barrier layer is the same as a material of a base of the active region.
  5. 5. The semiconductor structure of any one of claims 1 to 4, wherein the material of the barrier layer comprises silicon or silicon carbide.
  6. 6. The semiconductor structure of claim 1, wherein a doping element is present in the barrier layer, the doping element being either N-type or P-type.
  7. 7. The semiconductor structure of claim 1, wherein the substrate of the active region comprises a source terminal and a drain terminal, and wherein a side of the channel layer is in contact with a side of the barrier layer along an arrangement direction of the source terminal and the drain terminal.
  8. 8. The semiconductor structure of claim 1, wherein the barrier layer surrounds the channel layer sides.
  9. 9. The semiconductor structure of claim 1, wherein the material of the channel layer comprises silicon germanium or germanium.
  10. 10. A method of fabricating a semiconductor structure, comprising: Providing a substrate, wherein the substrate comprises an active region; Forming a channel layer, wherein the channel layer is positioned on the surface of the substrate of the active region; Forming a barrier layer, wherein the barrier layer is positioned on the surface of the substrate, the side surface of the channel layer is contacted with the side surface of the barrier layer, and the lattice constant of the material of the channel layer is larger than that of the material of the barrier layer and the substrate; The top surface of the barrier layer, which is far away from the substrate, is higher than the top surface of the channel layer, which is far away from the substrate, wherein the height difference between the top surface of the barrier layer and the top surface of the channel layer is 10A-100A; The bottom surface of the barrier layer is lower than the bottom surface of the channel layer, and the height difference between the bottom surface of the barrier layer and the bottom surface of the channel layer is 3-5 nm.
  11. 11. The method of claim 10, wherein the forming the channel layer and the barrier layer comprises: providing an initial substrate, and sequentially forming a semiconductor film and the gate structure on the surface of the initial substrate; etching to remove the semiconductor film exposed outside the grid structure; and forming the barrier layer, wherein the barrier layer is positioned on the surface of the initial substrate and on the side surface of the semiconductor film, the rest of the initial substrate is used as the substrate, and the rest of the semiconductor film is used as the channel layer.
  12. 12. The method of claim 11, wherein etching the initial substrate to a partial thickness forms a first recess while etching away the semiconductor film exposed outside the gate structure, and wherein the barrier layer further fills the first recess.
  13. 13. The method of any of claims 10 to 12, wherein the barrier layer is formed using a selective epitaxial growth process at a temperature of 800 ℃ to 850 ℃.
  14. 14. The method of claim 10, wherein the forming the channel layer and the barrier layer comprises: Providing a substrate; Patterning a portion of the thickness of the substrate to form a second recess in the substrate; forming the channel layer, wherein the channel layer is positioned in the second groove, and the height of the channel layer is smaller than or equal to the depth of the second groove along the direction vertical to the surface of the substrate; And doping the substrate with the partial thickness to form the barrier layer.

Description

Semiconductor structure and preparation method thereof Technical Field The embodiment of the disclosure relates to the field of semiconductors, in particular to a semiconductor structure and a preparation method. Background With the continuous development of integrated circuit technology and process technology, the feature size of transistor (MOS) devices is continuously reduced in order to improve the integration level of integrated circuits. Under the process nodes of high dielectric material metal gate (HKMG), fin transistor (Finfet) and the like, a series of problems need to be faced while improving the operating speed of the MOS device and reducing its power consumption. How to prevent the stress relaxation phenomenon of the channel layer due to the thermal effect and improve the stability of the semiconductor structure has become an important problem to be solved by those skilled in the art. Disclosure of Invention The embodiment of the disclosure provides a semiconductor structure and a preparation method thereof, which are at least beneficial to preventing the stress relaxation problem of a channel layer. According to some embodiments of the present disclosure, an aspect of the present disclosure provides a semiconductor structure including a substrate including an active region, a channel layer located on a substrate surface of the active region, a gate structure located on a channel layer surface, a barrier layer located on a substrate surface of the active region, a side of the barrier layer in contact with a side of the channel layer, a lattice constant of a material of the channel layer being larger than lattice constants of materials of the barrier layer and the substrate. According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a method for manufacturing a semiconductor structure, including providing a substrate including an active region, forming a channel layer on a surface of the substrate of the active region, forming a gate structure over the channel layer, forming a barrier layer on a surface of the substrate, a side surface of the channel layer contacting a side surface of the barrier layer, and a lattice constant of a material of the channel layer being greater than a lattice constant of a material of the barrier layer and the substrate. The technical scheme provided by the embodiment of the disclosure has at least the following advantages: In the semiconductor structure provided by the embodiment of the disclosure, the barrier layer is arranged on the surface of the substrate, the side surface of the channel layer is contacted with the side surface of the barrier layer, the barrier layer is formed on two sides of the channel layer, the lattice boundary of the material of the channel layer is fixed, and the deformation of the film layer of the channel layer is avoided, so that the stress relaxation phenomenon of the channel layer is prevented. In addition, the purpose of extruding the channel layer under the gate structure is achieved by utilizing the difference of the lattice constants of the material of the channel layer and the material of the blocking layer, and the compressive stress generated by the difference of the lattice constants can offset the stress relaxation phenomenon of part of the channel layer due to the thermal action, so that the lattice of the material of the channel layer cannot relax towards the periphery. Drawings One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise. One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically claimed, and in order to more clearly illustrate the embodiments of the present disclosure or the concepts of the conventional art, the drawings that are required to be utilized in the embodiments will be briefly described below, it will be apparent that the drawings in the following description are merely some embodiments of the present disclosure and that other drawings may be derived from these drawings by one of ordinary skill in the art without undue effort. Fig. 1 is a schematic structural diagram of a semiconductor structure according to an embodiment of the disclosure; Fig. 2 to fig. 4 are schematic structural diagrams corresponding to each step in a method for manufacturing a semiconductor structure according to an embodiment of the disclosure; fig. 5 to 10 are schematic structural diagrams corresponding to each step in a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure. Detailed Description As known from the background art, the conventional semiconductor structure may have a stress relaxation