CN-114792534-B - Dynamic trimming selection based on operating voltage levels of semiconductor devices and related methods and systems

Abstract

Dynamic trimming selection based on operating voltage levels of semiconductor devices and associated methods and systems are disclosed. Some semiconductor devices are expected to operate at two or more operating voltage levels. In some embodiments, the semiconductor device may be characterized to determine an optimal timing and/or voltage condition across multiple operating voltage levels. Thus, multiple sets of timing and/or voltage conditions may be identified depending on the operating voltage levels that may be stored in a non-volatile memory NVM array of the semiconductor device. During operation, the semiconductor device can determine the operating voltage level currently supplied to the semiconductor device and select one of the timing and/or voltage conditions stored in the NVM array such that the semiconductor device can operate at the optimal timing and/or voltage condition that has been predetermined for the semiconductor device operating at the operating voltage level.

Inventors

• C. G. viduwitt
• J.S. Rehmael

Assignees

• 美光科技公司

Dates

Publication Date

20260512

Application Date

20220106

Priority Date

20210126

Claims (19)

1. 1. A semiconductor device, comprising: A non-volatile memory NVM array configured to store a plurality of trim codes, wherein each trim code of the plurality of trim codes corresponds to one of a plurality of voltage level ranges of an operating voltage of the semiconductor device, and Peripheral circuitry coupled with the NVM array, the peripheral circuitry configured to: Determining that the operating voltage is within a range of voltage levels of the plurality of ranges; Selecting a trim code of the plurality of trim codes, the trim code corresponding to the voltage level range, and The trim code is transmitted to trim adjustment circuitry of the semiconductor device coupled to the peripheral circuitry.
2. 2. The semiconductor device of claim 1, wherein the plurality of voltage level ranges do not overlap one another.
3. 3. The semiconductor device of claim 1, wherein the peripheral circuitry is further configured to: The plurality of trim codes retrieved from the NVM array are stored in one or more internal latches of the semiconductor device, wherein selecting the trim codes corresponds to selecting the trim codes stored in the one or more internal latches.
4. 4. The semiconductor device of claim 1, wherein the peripheral circuitry comprises a voltage detection circuit configured to detect a voltage level of the operating voltage, and wherein determining that the operating voltage is within the range of voltage levels is based at least in part on the voltage detection circuit detecting the voltage level.
5. 5. The semiconductor device of claim 4, wherein the voltage detection circuit is configured to provide a stable indication of the voltage level range if the detected change in voltage level exceeds a boundary value of the voltage level range by less than a predetermined hysteresis threshold.
6. 6. The semiconductor device of claim 4, wherein the voltage detection circuit is coupled to a pad of the semiconductor device, the pad configured to supply the operating voltage to the semiconductor device.
7. 7. The semiconductor device of claim 6, wherein the voltage detection circuit is configured to detect the operating voltage at the pad in response to a predefined operation performed for the semiconductor device.
8. 8. The semiconductor device according to claim 1, further comprising: A mode register configured to indicate a voltage level of the operating voltage, wherein determining that the operating voltage is within the voltage level range is based at least in part on the mode register indicating the voltage level.
9. 9. The semiconductor device of claim 8, wherein a host device programs the mode register to indicate the voltage level, the host device being operably coupled with the semiconductor device.
10. 10. The semiconductor device of claim 1, wherein the trimming adjustment circuit is configured to adjust a set of timing and/or voltage conditions of one or more trimmable circuits of the semiconductor device based at least in part on receiving the trimming code from the peripheral circuitry.
11. 11. The semiconductor device of claim 10, wherein the set of timing and/or voltage conditions has been preconfigured to cause the one or more trimmable circuits to operate within the voltage level range of the operating voltage.
12. 12. The semiconductor device according to claim 1, further comprising: logic circuitry coupled to the NVM array, the logic circuitry configured to retrieve the plurality of trim codes from the NVM array and transmit the plurality of trim codes to one or more internal latches of the semiconductor device.
13. 13. A method of operating a semiconductor device, comprising: Determining that an operating voltage of the semiconductor device is within a voltage level range, wherein the voltage level range is one of a plurality of voltage level ranges of the operating voltage; selecting a trim code from a plurality of trim codes stored in a non-volatile memory NVM array of the semiconductor device, wherein each trim code of the plurality of trim codes corresponds to one voltage level range of the plurality of voltage level ranges and the selected trim code corresponds to the voltage level range, and The trim code is transmitted to a trim adjustment circuit of the semiconductor device.
14. 14. The method as recited in claim 13, further comprising: The plurality of trim codes retrieved from the NVM array are stored in one or more internal latches of the semiconductor device, wherein selecting the trim codes corresponds to selecting the trim codes stored in the one or more internal latches.
15. 15. The method of claim 13, wherein determining that the operating voltage of the semiconductor device is within the voltage level range includes: A voltage level at a pad of the semiconductor device is detected, the pad configured to supply the operating voltage to the semiconductor device.
16. 16. The method of claim 13, wherein determining that the operating voltage of the semiconductor device is within the voltage level range includes: An indication of the voltage level is received from a mode register of the semiconductor device, the mode register configured to store the indication of the voltage level.
17. 17. The method as recited in claim 13, further comprising: A set of timing and/or voltage conditions of one or more trimmable circuits of the semiconductor device is adjusted at the trim adjustment circuit based at least in part on receiving the trim code.
18. 18. A method of operating a semiconductor device, comprising: supplying a first voltage to an operating voltage of the semiconductor device, wherein the first voltage is included within a first voltage level range of a plurality of voltage level ranges of the operating voltage; determining a first set of timing and/or voltage conditions for one or more trimmable circuits of the semiconductor device operating at the first voltage; Generating a first trim code corresponding to the first set of timing and/or voltage conditions; storing the first trim code in a non-volatile memory NVM array of the semiconductor device; supplying a second voltage to the operating voltage, wherein the second voltage is included in a second voltage level range of the plurality of voltage level ranges, and the plurality of voltage level ranges corresponds to an entire voltage level range of the operating voltage and does not overlap each other; determining a second set of timing and/or voltage conditions for the one or more trimmable circuits operating at the second voltage; Generating a second trim code corresponding to the second set of timing and/or voltage conditions, and The second trim code is stored in the NVM array.
19. 19. The method as recited in claim 18, further comprising: Supplying a third voltage to the operating voltage; determining a third set of timing and/or voltage conditions for the one or more trimmable circuits operating at the third voltage; Generating a third trim code corresponding to the third set of timing and/or voltage conditions, and The third trim code is stored in the NVM array.

Description

Dynamic trimming selection based on operating voltage levels of semiconductor devices and related methods and systems Technical Field The present disclosure relates generally to semiconductor devices and, more particularly, to dynamic trimming selection based on operating voltages of semiconductor devices and associated methods and systems. Background Semiconductor devices are widely used to process information related to various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Some semiconductor devices are used to store information-e.g., memory devices. The memory device may be volatile or nonvolatile and may be of various types such as magnetic hard disk, random Access Memory (RAM), read Only Memory (ROM), dynamic RAM (DRAM), synchronous Dynamic RAM (SDRAM), and the like. Information is stored in various types of RAM by charging the memory cells to have different states. Improving RAM memory devices may generally include increasing memory cell density, increasing read/write speed or otherwise reducing operating latency, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among others. Disclosure of Invention According to an aspect of the present application, a semiconductor device is provided. The semiconductor device includes a non-volatile memory (NVM) array configured to store a plurality of trim codes, wherein each trim code of the plurality of trim codes corresponds to one of a plurality of voltage level ranges of an operating voltage of the semiconductor device, and peripheral circuitry coupled with the NVM array, the peripheral circuitry configured to determine that the operating voltage is within the plurality of ranges of voltage levels, select a trim code of the plurality of trim codes, the trim code corresponding to the voltage level range, and transmit the trim code to a trim adjustment circuit of the semiconductor device coupled to the peripheral circuitry. According to another aspect of the present application, a method of operating a semiconductor device is provided. The method includes determining that an operating voltage of the semiconductor device is within a voltage level range, wherein the voltage level range is one of a plurality of voltage level ranges of the operating voltage, selecting a trim code from a plurality of trim codes stored in a non-volatile memory (NVM) array of the semiconductor device, wherein each trim code of the plurality of trim codes corresponds to one of the plurality of voltage level ranges and the selected trim code corresponds to the voltage level range, and transmitting the trim code to a trim adjustment circuit of the semiconductor device. According to yet another aspect of the present application, a method is provided. The method includes supplying a first voltage to an operating voltage of a semiconductor device, determining a first set of timing and/or voltage conditions for one or more trimmable circuits of the semiconductor device to operate at the first voltage, generating a first trim code corresponding to the first set of timing and/or voltage conditions, storing the first trim code in a non-volatile memory (NVM) array of the semiconductor device, supplying a second voltage to the operating voltage, determining a second set of timing and/or voltage conditions for the one or more trimmable circuits to operate at the second voltage, generating a second trim code corresponding to the second set of timing and/or voltage conditions, and storing the second trim code in the NVM array. Drawings The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. FIG. 1 is a block diagram of a memory device showing various components for dynamic trimming selection based on operating voltage levels according to embodiments of the present disclosure. FIG. 2 is a flow chart of dynamic trim selection based on operating voltage levels according to an embodiment of the present disclosure. Fig. 3 is a block diagram schematically illustrating a memory system according to an embodiment of the present disclosure. Fig. 4 and 5 are flowcharts of methods of dynamic trimming selection based on operating voltage levels according to embodiments of the present disclosure. Detailed Description For some high performance memory systems, power consumption increases with increasing system rate. The increase in power consumption typically causes an increase in the operating temperature of memory devices (e.g., DRAMs) in the system. To meet the thermal boundaries of a memory device, it would be desirable to reduce or maintain power consumption while providing increased rates. To this end, the memory device may include higher performance Complementary Metal Oxide Semiconductor (CMOS) components and/or circuits capable of meeting a rate at a reduced operating v