CN-114816810-B - Device failure status reporting

Abstract

The present application relates to device failure status reporting. The host system may transmit a command to perform an operation to the memory system. The memory system may receive the command and identify a fault state associated with performing the operation. The memory system may transmit a message to the host system indicating the failure state. After the memory system transmits the message, the memory system may enter a secure mode of operation based on identifying the fault condition.

Inventors

• C. Atanasio
• C. Manganelli
• M. Yakulo
• P. Papa
• A. Eliso

Assignees

• 美光科技公司

Dates

Publication Date

20260505

Application Date

20220120

Priority Date

20210122

Claims (20)

1. 1. An apparatus, comprising: Memory device, and Control circuitry coupled with the memory device and configured to cause the apparatus to: Receiving a command to perform an operation from a host system; De-allocating buffer resources associated with data from the host system; receiving a notification based at least in part on deallocating the buffer resource; Identifying a fault state of the device associated with performing the operation based at least in part on receiving the command and receiving the notification; Transmitting a message from the memory device to the host system indicating the failure state based at least in part on identifying the failure state, wherein the message includes an indication of the command, and A safe mode of operation is entered based at least in part on identifying the fault condition.
2. 2. The apparatus of claim 1, wherein the control circuit is further configured to cause the apparatus to: generating the message indicative of the fault state based at least in part on identifying the fault state, wherein transmitting the message is based at least in part on generating the message.
3. 3. The apparatus of claim 1, wherein the control circuit is further configured to cause the apparatus to: Generating a code associated with the fault state that signals the host system that the fault state is present based at least in part on identifying the fault state, wherein the message includes the code.
4. 4. The apparatus of claim 1, wherein the control circuit is further configured to cause the apparatus to: Information associated with the fault state is identified based at least in part on identifying the fault state, wherein the message includes one or more bits indicating the information associated with the fault state.
5. 5. The apparatus of claim 4, wherein the information associated with the fault condition comprises a time at which the fault condition occurred, a duration of the fault condition, a temperature of the apparatus, or a combination thereof.
6. 6. The apparatus of claim 1, wherein the control circuit is further configured to cause the apparatus to: A timeout state is identified based at least in part on identifying the fault state, wherein transmitting the message is based at least in part on identifying the timeout state.
7. 7. The apparatus of claim 1, wherein the control circuit is further configured to cause the apparatus to: The fault state and information associated with the fault state are stored in a shared memory associated with the apparatus based at least in part on identifying the fault state.
8. 8. The apparatus of claim 1, wherein the control circuit is further configured to cause the apparatus to: exit the secure mode of operation after expiration of a duration of time, and A second command to perform a second operation is received from the host system based at least in part on exiting the secure mode of operation.
9. 9. The apparatus of claim 1, wherein the control circuit is further configured to cause the apparatus to: avoiding performing the operation based at least in part on entering the secure mode of operation.
10. 10. The apparatus of claim 1, wherein the command is a write command, a cache command, a read command, or a combination thereof.
11. 11. The device of claim 1, wherein the fault condition comprises a hardware exception associated with the device, a firmware stuck state of the device, an operating condition of the device that satisfies a threshold, a capacity operation of the device, a resource limitation of the device, a background operation, a temperature detection operation, a refresh operation, or a combination thereof.
12. 12. A non-transitory computer-readable medium storing code comprising instructions that when executed by a processor of an electronic device cause the electronic device to: Receiving a command to perform an operation from a host system; De-allocating buffer resources associated with data from the host system; receiving a notification based at least in part on deallocating the buffer resource; identifying a fault state of a device associated with performing the operation based at least in part on receiving the command and receiving the notification; Transmitting a message from a memory system to the host system indicating the failure state based at least in part on identifying the failure state, wherein the message includes an indication of the command, and A safe mode of operation is entered based at least in part on identifying the fault condition.
13. 13. The non-transitory computer-readable medium of claim 12, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: generating the message indicative of the fault state based at least in part on identifying the fault state, wherein transmitting the message is based at least in part on generating the message.
14. 14. The non-transitory computer-readable medium of claim 12, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: Generating a code associated with the fault state that signals the host system that the fault state is present based at least in part on identifying the fault state, wherein the message includes the code.
15. 15. The non-transitory computer-readable medium of claim 12, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: Information associated with the fault state is identified based at least in part on identifying the fault state, wherein the message includes one or more bits indicating the information associated with the fault state.
16. 16. The non-transitory computer-readable medium of claim 15, wherein the information associated with the fault state comprises a time at which the fault state occurred, a duration of the fault state, a temperature of the memory system, or a combination thereof.
17. 17. The non-transitory computer-readable medium of claim 12, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: A timeout state is identified based at least in part on identifying the fault state, wherein transmitting the message is based at least in part on identifying the timeout state.
18. 18. A method performed at a memory system, comprising: receiving a command from a host system to cause the memory system to perform an operation; De-allocating buffer resources associated with data from the host system; receiving a notification based at least in part on deallocating the buffer resource; identifying, by the memory system, a failure state of the memory system associated with the operation based at least in part on receiving the command and receiving the notification; Transmitting a message from the memory system to the host system indicating the failure state based at least in part on identifying the failure state, wherein the message includes an indication of the command, and A secure mode of operation is entered by the memory system based at least in part on identifying the fault condition.
19. 19. The method as recited in claim 18, further comprising: generating the message indicative of the fault state based at least in part on identifying the fault state, wherein transmitting the message is based at least in part on generating the message.
20. 20. The method as recited in claim 18, further comprising: Generating a code associated with the fault state that signals the host system that the fault state is present based at least in part on identifying the fault state, wherein the message includes the code.

Description

Device failure status reporting Cross reference to related applications This patent application claims priority to U.S. provisional patent application No. 63/140,378 entitled "device failure status report (DEVICE FAULT CONDITION REPORTING)" filed by atanasiow (ATTANASIO) et al at 2021, month 1, 22, which is assigned to the assignee hereof and expressly incorporated herein by reference in its entirety. Technical Field The technical field relates to device fault status reporting. Background Memory devices are widely used to store information in a variety of electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device to various states. For example, a binary memory cell may be programmed to one of two support states, typically corresponding to a logic 1 or a logic 0. In some examples, a single memory cell may support more than two possible states, any of which may be stored by the memory cell. To access information stored by the memory device, the component may read or sense the state of one or more memory cells within the memory device. To store information, a component may write or program one or more memory cells within a memory device to a corresponding state. There are various types of memory devices including magnetic hard disks, random Access Memory (RAM), read Only Memory (ROM), dynamic RAM (DRAM), synchronous Dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase Change Memory (PCM), 3-dimensional cross point memory (3D cross point), NOR and NAND memory devices, and others. The memory device may be volatile or nonvolatile. Volatile memory cells (e.g., DRAM cells) may lose their programmed state over time unless they are periodically refreshed by an external power source. Even without an external power source, a non-volatile memory cell (e.g., a NAND memory cell) can maintain its programmed state for an extended period of time. Disclosure of Invention An apparatus is described. The apparatus may include a memory device and a control circuit coupled with the memory device. The control circuitry may be configured to cause the apparatus to receive a command from a host system to perform an operation, identify a fault state of the apparatus associated with performing the operation based on receiving the command, transmit a message to the host system indicating the fault state based on identifying the fault state, and enter a secure mode of operation based on identifying the fault state. A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to receive a command from a host system to perform an operation, identify a failure state of a memory system associated with performing the operation based on receiving the command, transmit a message to the host system indicating the failure state based on identifying the failure state, and enter a secure mode of operation based on identifying the failure state. A method performed by a memory system is described. The method may include receiving a command from a host system to cause the memory system to perform an operation, identifying a failure state of the memory system associated with performing the operation based on receiving the command, transmitting a message to the host system indicating the failure state based on identifying the failure state, and entering, by the memory system, a secure mode of operation based on identifying the failure state. Drawings Fig. 1 illustrates an example of a system supporting device failure status reporting according to examples disclosed herein. Fig. 2 illustrates an example of a flow chart supporting device failure status reporting according to examples disclosed herein. Fig. 3 illustrates an example of a message supporting device failure status reporting according to examples disclosed herein. FIG. 4 shows a block diagram of a memory system supporting device failure status reporting according to examples disclosed herein. Fig. 5 shows a flow chart illustrating a method or methods of supporting device failure status reporting in accordance with examples disclosed herein. Detailed Description The memory system may experience a fault condition associated with performing operations of the memory system. When a fault condition occurs, the software or firmware (or hardware) of the memory system may cease to operate (or may be suspended) as intended. If the memory system does not perform the intended function within a period of time, the host system may identify a timeout state of the memory system and request a memory system reset. For example, a failure state (e.g., a message indicating a failure state) may not be communicated to the host system, but rather the host system may perform a