CN-114823469-B - Vacuum bonding component and preparation method of chip package

CN114823469BCN 114823469 BCN114823469 BCN 114823469BCN-114823469-B

Abstract

The invention provides a vacuum bonding component and a preparation method of a chip package, wherein the bonding component comprises a sucker carrier and a sealing gasket, the sucker carrier is provided with a bearing surface and a non-bearing surface, a negative pressure adsorption channel is arranged on the bearing surface, a diversion channel communicated with the negative pressure adsorption channel is arranged in the sucker carrier, an air suction channel is arranged on the non-bearing surface, the air suction channel is communicated with the diversion channel, the sealing gasket with an airtight through hole is detachably arranged on the bearing surface, the airtight through hole is communicated with the negative pressure adsorption channel, and a bearing area for bearing the chip package is formed.

Inventors

DING XIAOCHUN
LI ZONGYI
Liang xinfu
GUO LIANGKUI
WANG JIAWEI

Assignees

长电集成电路(绍兴)有限公司

Dates

Publication Date: 20260505
Application Date: 20220418

Claims (9)

1. A method of manufacturing a chip package, the method comprising: providing a vacuum bonding member; providing a chip, wherein an active surface of the chip is provided with a conductive interconnection column, and a passive surface of the chip is a crystalline silicon base surface with a mirror effect, which is obtained by performing precise grinding treatment; Vacuumizing the vacuum bonding component through an air suction channel; sequentially preparing a metal wiring layer, a bonding pad, a conductive column and a tin-base alloy solder ball on the conductive interconnection column; removing the vacuum bonding component by removing the vacuum adsorption force through the air suction channel to obtain a chip package; the vacuum bonding member includes: A suction cup carrier and a sealing gasket; The sucker carrier is provided with a bearing surface and a non-bearing surface, a negative pressure adsorption channel is arranged on the bearing surface, a diversion channel communicated with the negative pressure adsorption channel is arranged in the sucker carrier, an air suction channel is arranged on the non-bearing surface, and the air suction channel is communicated with the diversion channel; The sealing gasket is provided with an airtight through hole and is detachably arranged on the bearing surface, the airtight through hole is communicated with the negative pressure adsorption channel to form a bearing area for bearing the chip packaging body, and the passive surface of the chip is placed in the bearing area of the vacuum bonding component.
2. The method of manufacturing a chip package according to claim 1, wherein the sealing gasket comprises an elastic material.
3. The method of manufacturing a chip package according to claim 1, wherein sequentially manufacturing a metal wiring layer, a pad, a conductive pillar, and a tin-based alloy solder ball on the conductive interconnect pillar, comprises: filling the chip with a plastic package material to form an encapsulation layer, so that the upper surface of the encapsulation layer and the top ends of the conductive interconnection columns are in the same horizontal plane; and sequentially preparing a metal wiring layer, a bonding pad, a conductive column and a tin-base alloy solder ball on the upper surface of the encapsulation layer.
4. The method of manufacturing a chip package according to claim 1, wherein after sequentially manufacturing a metal wiring layer, a pad, a conductive pillar, and a tin-based alloy solder ball on the conductive interconnect pillar, the method further comprises: and sticking a protective film on the tin-base alloy solder balls.
5. A method of manufacturing a chip package, the method comprising: providing a vacuum bonding member; the vacuum bonding member includes: A suction cup carrier and a sealing gasket; The sucker carrier is provided with a bearing surface and a non-bearing surface, a negative pressure adsorption channel is arranged on the bearing surface, a diversion channel communicated with the negative pressure adsorption channel is arranged in the sucker carrier, an air suction channel is arranged on the non-bearing surface, and the air suction channel is communicated with the diversion channel; The sealing gasket is provided with an airtight through hole and is detachably arranged on the bearing surface, wherein the airtight through hole is communicated with the negative pressure adsorption channel to form a bearing area for bearing the chip packaging body; providing a metal foil, and covering the metal foil on a bearing area of the vacuum bonding component; providing a chip, wherein a conductive interconnection column is arranged on an active surface of the chip; preparing a metal wiring layer on the metal foil, arranging the chip on the metal wiring layer, and conducting and interconnecting conductive interconnection columns on the active surface of the chip and the metal wiring layer; Vacuumizing the vacuum bonding component through an air suction channel; Removing the vacuum bonding component through the air suction channel to obtain a pre-package body; and preparing a conductive column and a tin-base alloy solder ball on the surface of the metal foil on the pre-package body to obtain the chip package body.
6. The method of manufacturing a chip package according to claim 5, wherein before the vacuum suction force is released through the suction channel, the method further comprises: And filling the chip with a plastic packaging material to form an encapsulation layer, so that the upper surface of the encapsulation layer and the passive surface of the chip are in the same horizontal plane.
7. The method of manufacturing a chip package according to claim 6, wherein before the chip is filled with the molding compound to form an encapsulation layer, the method further comprises: And (3) performing bottom filling on the conductive interconnection column to obtain an underfill layer.
8. The method of manufacturing a chip package according to claim 6, wherein the step of manufacturing a conductive pillar and a tin-based alloy solder ball on the surface of the metal foil on the pre-package to obtain the chip package comprises: Preparing a layer of organic solder mask on the surface of the metal foil on the pre-packaging body; and carrying out photoetching opening, cleaning and copper electroplating processes on the organic solder mask to prepare a conductive column and a tin-base alloy solder ball, thereby obtaining the chip package.
9. The method of claim 6, wherein the sealing pad comprises an organic silicone, or/and the metal foil comprises a copper foil, or/and the encapsulating layer comprises an epoxy resin.

Description

Vacuum bonding component and preparation method of chip package Technical Field The invention relates to the technical field of chip packaging, in particular to a preparation method applicable to vacuum bonding components and chip packaging bodies. Background In the existing industrial production, in the preparation process of the chip fan-out packaging structure, a carrier plate with higher Young modulus is added as a process carrier of the chip packaging process, so that a mechanical supporting force for resisting gravity is provided for the preparation of a plurality of high-density RDL layers, a layer of ultraviolet light bonding adhesive film is generally attached to the carrier plate, after the chip packaging process is finished, ultraviolet light acts on a photosensitizer in the bonding adhesive film, so that the bonding adhesive film is combined with the carrier and the chip packaging matrix Jie Jian, and the purpose of separating the carrier plate from the chip packaging body is achieved. However, in the process of debonding, the components of the bonding adhesive layer cannot sufficiently react with ultraviolet light, so that after debonding, the bonding adhesive generally remains on the chip package, which has an adverse effect on the signal transmission and power supply of the chip and the reliability of the chip package. Therefore, the chip packaging method in the prior art has the problem of residual bonding glue, which has adverse effects on signal transmission and power supply of the chip and reduces the reliability of the chip packaging body. Disclosure of Invention Aiming at the defects existing in the prior art, the vacuum bonding component and the preparation method of the chip packaging body solve the problem that residual bonding glue exists in the chip packaging body in the prior art, improve the reliability of the chip packaging body, and reduce the cost of raw materials and the process control cost of de-bonding. The invention provides a vacuum bonding component which comprises a sucker carrier and a sealing gasket, wherein the sucker carrier is provided with a bearing surface and a non-bearing surface, a negative pressure adsorption channel is arranged on the bearing surface, a flow guide channel communicated with the negative pressure adsorption channel is arranged in the sucker carrier, an air suction channel is arranged on the non-bearing surface and is communicated with the flow guide channel, the sealing gasket is provided with an airtight through hole and is detachably arranged on the bearing surface, and the airtight through hole is communicated with the negative pressure adsorption channel to form a bearing area for bearing a chip package body. Optionally, the sealing gasket comprises an elastic material. The invention provides a preparation method of a chip package, which comprises the steps of providing a vacuum bonding component, providing a chip, placing a passive surface of the chip in a bearing area of the vacuum bonding component, wherein an electric conduction interconnection column is arranged on the active surface of the chip, the passive surface of the chip is a crystalline silicon base surface with a mirror effect obtained by precise grinding, vacuumizing the vacuum bonding component through an air suction channel, sequentially preparing a metal wiring layer, a bonding pad, a conductive column and tin-based alloy solder balls on the electric conduction interconnection column, and removing the vacuum bonding component through the air suction channel to obtain the chip package. The method comprises the steps of filling a chip with a plastic package material to form an encapsulation layer, enabling the upper surface of the encapsulation layer and the top ends of the conductive interconnection columns to be in the same horizontal plane, and sequentially preparing a metal wiring layer, a bonding pad, a conductive column and a tin-base alloy solder ball on the upper surface of the encapsulation layer. Optionally, after sequentially preparing the metal wiring layer, the bonding pad, the conductive post and the tin-based alloy solder ball on the conductive interconnection post, the method further comprises attaching a protective film on the tin-based alloy solder ball. The invention provides a preparation method of a chip package, which comprises the steps of providing a vacuum bonding component, providing a metal foil, covering the metal foil on a bearing area of the vacuum bonding component, vacuumizing the vacuum bonding component through an air suction channel, preparing a metal wiring layer on the metal foil, conducting and interconnecting a conductive interconnection column on an active surface of a chip and the metal wiring layer, removing the vacuum bonding component through the air suction channel to obtain a pre-package, and preparing the conductive column and a tin-base alloy solder ball on the surface of the metal foil on the pre-package to obtain the chip p