CN-114823484-B - Semiconductor structure and forming method thereof

Abstract

A semiconductor structure and a forming method thereof are provided, wherein a dielectric layer is formed on a substrate, an interconnection structure penetrating through the dielectric layer is formed in the dielectric layer, the interconnection structure comprises a first interconnection opening and a second interconnection opening which are isolated, the opening size of the first interconnection opening is smaller than that of the second interconnection opening, a first interconnection structure is formed in the first interconnection opening, a second interconnection structure is formed in the second interconnection opening, the resistivity of a material of the second interconnection structure is smaller than that of a material of the first interconnection structure, and the gap filling capacity of the material of the first interconnection structure is larger than that of the material of the second interconnection structure. The invention improves the gap filling performance of the interconnection structure material and simultaneously ensures the conductive performance of the interconnection structure through the formation of the first interconnection structure and the second interconnection structure, thereby improving the electrical performance and the reliability of the device, such as the rear-section electrical performance, electromigration (electro migration, EM) performance and the like.

Inventors

• LIU JIQUAN

Assignees

• 中芯国际集成电路制造(上海)有限公司
• 中芯国际集成电路制造(上海)有限公司
• 中芯国际集成电路制造(北京)有限公司
• 中芯国际集成电路制造(北京)有限公司

Dates

Publication Date

20260421

Application Date

20210119

Priority Date

20210119

Claims (18)

1. 1. A method of forming a semiconductor structure, comprising: Providing a substrate, wherein a dielectric layer is formed on the substrate, an interconnection opening penetrating through the dielectric layer is formed in the dielectric layer, the interconnection opening comprises a first interconnection opening and a second interconnection opening which are isolated, and the opening size of the first interconnection opening is smaller than that of the second interconnection opening; Forming a first interconnection structure in the first interconnection opening and forming a second interconnection structure in the second interconnection opening; wherein the resistivity of the second interconnect structure material is less than the resistivity of the first interconnect structure material, and the gap filling capability of the first interconnect structure material is greater than the gap filling capability of the second interconnect structure material; before forming the first interconnection structure and the second interconnection structure, the forming method further comprises the steps of forming an infiltration layer at the bottom and the side wall of the interconnection opening; forming a first interconnect structure in the first interconnect opening using a selective forming process; after forming the first interconnect structure, the forming method further includes removing the inhibit layer; And after removing the inhibition layer, forming a second interconnection structure in the second interconnection opening.
2. 2. The method of claim 1, wherein the wetting layer is formed by a chemical vapor deposition process.
3. 3. The method of claim 1, wherein the accommodating layer is formed by surface treating the accommodating layer using a chemical immersion process.
4. 4. The method of forming a semiconductor structure of claim 1, wherein the inhibiting layer is a layer of organic polymer molecules having a physical diameter that is greater than an opening size of the first interconnect opening and less than an opening size of the second interconnect opening.
5. 5. The method of claim 4, wherein the physical diameter of molecules in the organic polymer molecular layer is greater than or equal to 10nm.
6. 6. The method of claim 4, wherein the material of the organic polymer molecular layer comprises at least two elements of C, N, H and O.
7. 7. The method of claim 4, wherein the organic polymer molecular layer material comprises one or both of poly-3-bipyridine and polyethylene glycol-like.
8. 8. The method of forming a semiconductor structure of claim 1, wherein the thickness of the inhibit layer is from 0.5nm to 5nm.
9. 9. The method of forming a semiconductor structure of claim 1, wherein the inhibiting layer is removed using a drying process.
10. 10. The method of forming a semiconductor structure of claim 1, wherein the selective forming process comprises a selective deposition process and a selective electroplating process.
11. 11. The method of forming a semiconductor structure of claim 1, wherein a second interconnect structure is formed at the second interconnect opening using an electrochemical plating process.
12. 12. The method of forming a semiconductor structure of claim 1, wherein a material of the first interconnect structure comprises one or more of Co, W, mo, and Ru and a material of the second interconnect structure comprises one or more of Cu, al, ag, and Au.
13. 13. The method of forming a semiconductor structure of claim 1, wherein before forming the wetting layer at the bottom and sidewalls of the interconnect opening, the method further comprises forming a barrier layer at the bottom and sidewalls of the interconnect opening.
14. 14. A semiconductor structure, comprising: a substrate; A dielectric layer on the substrate; An interconnect opening penetrating the dielectric layer, the interconnect opening comprising a first interconnect opening and a second interconnect opening that are isolated, the first interconnect opening having an opening size that is smaller than an opening size of the second interconnect opening; A first interconnect structure located in the first interconnect opening; a second interconnect structure located in the second interconnect opening; Wherein the resistivity of the second interconnect structure material is less than the resistivity of the first interconnect structure material, the gap filling capability of the first interconnect structure material being greater than the gap filling capability of the second interconnect structure material; an wetting layer located at the bottom and sidewalls of the interconnect opening; The first interconnection structure is positioned in the first interconnection opening formed with the wetting layer and is in contact with the wetting layer; the second interconnection structure is positioned in the second interconnection opening formed with the wetting layer; and no material residue of the first interconnection structure exists between the second interconnection structure and the wetting layer.
15. 15. The semiconductor structure of claim 14, wherein a material of the wetting layer comprises one or more of Co and Ru.
16. 16. The semiconductor structure of claim 14, wherein a material of the first interconnect structure comprises one or more of Co, W, mo, and Ru and a material of the second interconnect structure comprises one or more of Cu, al, ag, and Au.
17. 17. The semiconductor structure of claim 14, further comprising a barrier layer between a bottom of the interconnect opening and the wetting layer, and between sidewalls of the interconnect opening and the wetting layer.
18. 18. The semiconductor structure of claim 17, wherein the material of the barrier layer comprises one or more of TiN, taN, tiSiN, taSiN, ti and Ta.

Description

Semiconductor structure and forming method thereof Technical Field Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same. Background With the continued development of integrated circuit fabrication technology, the demands on the degree of integration and performance of integrated circuits are becoming ever higher. In order to improve the integration level and reduce the cost, the critical dimensions of the components are continuously reduced, and the circuit density inside the integrated circuit is increasingly high, so that the wafer surface cannot provide enough area to manufacture the required interconnection line. In order to meet the requirements of the interconnect lines with reduced critical dimensions, the conduction between different metal layers or metal layers and the substrate is realized through an interconnection structure. Along with the advancement of technology nodes, the size of an interconnection structure becomes smaller and smaller, and correspondingly, the process difficulty of forming the interconnection structure is also larger and larger, and the formation quality of the interconnection structure has a great influence on the electrical performance of a back end of line (BEOL) and the reliability of a device, and the normal operation of a semiconductor device can be influenced when the formation quality of the interconnection structure is serious. Disclosure of Invention The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, which balance the filling capacity of metal to an interconnection opening and the resistivity of the whole device, and improve the electrical performance and the reliability of the device. In order to solve the problems, the embodiment of the invention provides a method for forming a semiconductor structure, which comprises the steps of providing a substrate, forming a dielectric layer on the substrate, forming an interconnection structure penetrating through the dielectric layer in the dielectric layer, and forming a first interconnection opening and a second interconnection opening which are isolated, wherein the opening size of the first interconnection opening is smaller than that of the second interconnection opening, forming a first interconnection structure in the first interconnection opening and a second interconnection structure in the second interconnection opening, wherein the resistivity of a material of the second interconnection structure is smaller than that of the material of the first interconnection structure, and the gap filling capacity of the material of the first interconnection structure is larger than that of the material of the second interconnection structure. Optionally, before forming the first interconnection structure and the second interconnection structure, the forming method further comprises the steps of forming an infiltration layer at the bottom and the side wall of the interconnection opening, forming a suppression layer covering the infiltration layer in the second interconnection opening, forming the first interconnection structure in the first interconnection opening by adopting a selective forming process, removing the suppression layer after forming the first interconnection structure, and forming the second interconnection structure in the second interconnection opening after removing the suppression layer. Optionally, a chemical vapor deposition process is used to form the wetting layer. Optionally, a chemical infiltration process is adopted to carry out surface treatment on the infiltration layer to form the inhibition layer. Optionally, the inhibiting layer is an organic polymer molecular layer, and a physical diameter of a molecule in the organic polymer molecular layer is greater than an opening size of the first interconnection opening and less than an opening size of the second interconnection opening. Optionally, the physical diameter of the molecules in the organic polymer molecular layer is greater than or equal to 10nm. Optionally, the material of the organic polymer molecular layer comprises at least two elements of C, N, H and O. Optionally, the organic polymer molecular layer material comprises one or two of poly (3-bipyridine) and polyethylene glycol-like. Optionally, the thickness of the inhibition layer is 0.5nm to 5nm. Optionally, a drying process is used to remove the inhibition layer. Optionally, the selective forming process includes a selective deposition process and a selective electroplating process. Optionally, a second interconnect structure is formed at the second interconnect opening using an electrochemical plating process. Optionally, the material of the first interconnection structure includes one or more of Co, W, mo and Ru, and the material of the second interconnection structure includes one or more of Cu, al, ag an