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CN-114824016-B - LED epitaxial wafer and manufacturing method thereof

CN114824016BCN 114824016 BCN114824016 BCN 114824016BCN-114824016-B

Abstract

The application provides an LED epitaxial wafer and a manufacturing method thereof, the N-type GaN layer of the LED epitaxial wafer comprises an N_SL layer and an N_bulk layer. The N_SL layer comprises a first N_SL layer and a second N_SL layer, the first N_SL layer and the second N_SL layer are sequentially and circularly arranged from bottom to top, and the N_bulk layer comprises a first N_bulk layer and a second N_bulk layer. The N_SL layer and the N_bulk layer are equivalent to form a plurality of capacitor structures, the silicon doping degree of different concentrations enhances current diffusion, and the antistatic capability of the LED epitaxial wafer is improved. The dislocation density of the grown quantum well light-emitting layer is reduced by the arrangement of the N_SL layer and the N_bulk layer, and the lattice quality of the quantum well light-emitting layer is improved. In the manufacturing process of the LED epitaxial wafer, the SiH 4 valve group of MOCVD equipment does not need higher switching frequency, the service life of the SiH 4 valve group is prolonged, and the production cost is reduced.

Inventors

  • WANG WENJUN
  • JIANG HAN
  • LI GUOCHANG
  • XU YANGYANG
  • CHENG HU
  • YUAN SHUWEI

Assignees

  • 聚灿光电科技股份有限公司

Dates

Publication Date
20260512
Application Date
20220429

Claims (7)

  1. 1. The LED epitaxial wafer comprises a substrate, a buffer layer, a U-shaped GaN layer, an N-shaped GaN layer, a quantum well luminous layer, a P-shaped electron blocking layer and a P-shaped GaN layer which are sequentially stacked, and is characterized in that the N-shaped GaN layer comprises an N_SL layer and an N_bulk layer arranged on the N_SL layer, the N_SL layer and the N_bulk layer equivalently form a plurality of capacitor structures, the electron transmission rate is accelerated through the potential difference between two ends of the capacitor, so that the electron concentration of the quantum well luminous layer is improved, the lattice mismatch with the U-shaped GaN layer is gradually reduced, and the dislocation density of the quantum well luminous layer is reduced, wherein the thickness of the N_SL layer is smaller than that of the N_bulk layer; The N_SL layers comprise a plurality of first N_SL layers and a plurality of second N_SL layers, wherein the N_bulk layers comprise a first N_bulk layer and a second N_bulk layer arranged on the first N_bulk layer; the silicon doping concentration of the first N_SL layer is smaller than that of the second N_SL layer, the silicon doping concentration of the first N_bulk layer is larger than that of the second N_bulk layer, and the silicon doping concentration of the first N_SL layer is smaller than that of the second N_bulk layer; The first N_SL layer and the second N_SL layer are sequentially and circularly arranged from bottom to top, and the cycle times are between 10 and 20.
  2. 2. The LED epitaxial wafer of claim 1, wherein the first n_sl layer has a silicon doping concentration of between 1 x 10 18 ～5×10 18 /cm -3 , the second n_sl layer has a silicon doping concentration of between 1 x 10 19 ～3×10 19 /cm -3 , the first n_bulk layer has a silicon doping concentration of between 1 x 10 19 ～3×10 19 /cm -3 , and the second n_bulk layer has a silicon doping concentration of between 5 x 10 18 ～1×10 19 /cm -3 .
  3. 3. The LED epitaxial wafer of claim 2, wherein the first N_SL layer has a thickness of 15-20 nm, the second N_SL layer has a thickness of 30-35 nm, and the N_SL layer has a thickness of 450-550 nm.
  4. 4. The LED epitaxial wafer of claim 2, wherein the first N_bulk layer has a thickness of 500-600 nm, the second N_bulk layer has a thickness of 500-600 nm, and the N_bulk layer has a thickness of 1000-1200 nm.
  5. 5. The LED epitaxial wafer of claim 1, wherein the quantum well light emitting layer comprises a GaN layer and an In x Ga 1-x N layer arranged periodically, x is set to be between 0.2 and 0.3, the number of periods is between 7 and 12, the thickness of the GaN layer is between 8 and 12nm, and the thickness of the In x Ga 1-x N layer is between 2 and 5 nm.
  6. 6. A method for manufacturing an LED epitaxial wafer, for manufacturing the LED epitaxial wafer according to any one of claims 1 to 5, comprising: preparing a substrate, and growing a buffer layer on the substrate, wherein the growth temperature of the buffer layer is 800-1100 ℃; growing a U-shaped GaN layer on the buffer layer, wherein the growth temperature of the U-shaped GaN layer is 1000-1400 ℃; Sequentially and circularly growing a first N_SL layer and a second N_SL layer on the U-shaped GaN layer to obtain an N_SL layer, wherein the cycle number is 10-20, the growth temperature of the first N_SL layer is 1000-1200 ℃, the growth thickness of the first N_SL layer is 15-20 nm, the growth temperature of the second N_SL layer is 1000-1200 ℃, and the growth thickness of the second N_SL layer is 30-35 nm; Growing a first N_bulk layer on the N_SL layer, wherein the growth temperature of the first N_bulk layer is 1000-1200 ℃, and the growth thickness of the first N_bulk layer is 500-600 nm; Growing a second N_bulk layer on the first N_bulk layer, wherein the growth temperature of the second N_bulk layer is 900-1100 ℃, and the growth thickness of the second N_bulk layer is 500-600 nm; growing a quantum well light-emitting layer on the second N_bulk layer, wherein the growth temperature of the quantum well light-emitting layer is 700-800 ℃; growing a P-type electron blocking layer on the quantum well light-emitting layer, wherein the growth temperature of the P-type electron blocking layer is 800-1000 ℃; And growing a P-type GaN layer on the P-type electron blocking layer, wherein the growth temperature of the P-type GaN layer is 900-1100 ℃.
  7. 7. The method of manufacturing an LED epitaxial wafer of claim 6, wherein the first n_sl layer has a silicon doping concentration of between 1 x 10 18 ～5×10 18 /cm -3 , the second n_sl layer has a silicon doping concentration of between 1 x 10 19 ～3×10 19 /cm -3 , the first n_bulk layer has a silicon doping concentration of between 1 x 10 19 ～3×10 19 /cm -3 , and the second n_bulk layer has a silicon doping concentration of between 5 x 10 18 ～1×10 19 /cm -3 .

Description

LED epitaxial wafer and manufacturing method thereof Technical Field The application relates to the technical field of LEDs, in particular to an LED epitaxial wafer and a manufacturing method thereof. Background An LED (Light-Emitting Diode) is a semiconductor Light Emitting device that converts electric energy into Light energy. The LED epitaxial wafer refers to a specific single crystal thin film grown on a substrate piece heated to a proper temperature. Referring to fig. 1, an led epitaxial wafer generally includes a substrate, a buffer layer, a U-type GaN layer, an N-type GaN layer, a quantum well light emitting layer, and a P-type GaN layer, which are sequentially disposed from bottom to top. The growth of the LED epitaxial wafer is mainly realized by MOCVD (Metal-organic Chemical Vapor Depos ition, metal organic compound chemical vapor deposition) equipment. The N-type GaN layer structure of the LED epitaxial wafer grown by MOCVD equipment comprises an N_bulk structure and an N_SL structure. The N_bulk structure can provide higher electron concentration, but has larger lattice mismatch with the U-shaped GaN layer on the lower layer and the quantum well light-emitting layer on the upper layer, and the crystal quality of the quantum well light-emitting layer is affected. Compared with the N_bulk structure, the N_SL structure can effectively reduce lattice mismatch of the N-type GaN layer and the lower U-type GaN layer, but the N_SL structure can cause larger luminous voltage fluctuation due to N electrode etching difference. In addition, in the growth process, the SiH 4 valve group of the MOCVD equipment needs higher switching frequency, so that the service life of the SiH 4 valve group is reduced, and the production cost is increased. In addition, in the processes of manufacturing, installation and use, etc., the LED is inevitably affected by static electricity to generate induced charges, and if the induced charges cannot be released in time, higher voltages are formed at two ends of the PN junction. The traditional LED epitaxial wafer has poor antistatic capability, and when the voltage exceeds the maximum bearing value of the LED epitaxial wafer, electrostatic charges are discharged at two ends of a PN junction in extremely short moment, so that the PN junction is broken down, and the LED is invalid. Disclosure of Invention The application provides an LED epitaxial wafer and a manufacturing method thereof, which are used for solving the problems of large lattice mismatch, high production cost and poor antistatic capability of the traditional LED epitaxial wafer. On one hand, the application provides an LED epitaxial wafer, which comprises a substrate, a buffer layer, a U-shaped GaN layer, an N-shaped GaN layer, a quantum well luminescent layer, a P-shaped electron blocking layer and a P-shaped GaN layer which are sequentially stacked. The N-type GaN layer comprises an N_SL layer and an N_bulk layer arranged on the N_SL layer, wherein the thickness of the N_SL layer is smaller than that of the N_bulk layer. The N_SL layer comprises a plurality of first N_SL layers and a plurality of second N_SL layers. The N_bulk layer comprises a first N_bulk layer and a second N_bulk layer arranged on the first N_bulk layer. The first n_sl layer has a silicon doping concentration less than a silicon doping concentration of the second n_sl layer. The silicon doping concentration of the first N_bulk layer is greater than the silicon doping concentration of the second N_bulk layer. The silicon doping concentration of the first N_SL layer is smaller than that of the second N_bulk layer. And the N_SL layer and the N_bulk layer are equivalent to form a plurality of capacitor structures, the silicon doping degree of different concentrations enhances current diffusion, and the antistatic capability of the LED epitaxial wafer is improved. The N_SL layer and the N_bulk layer are structurally arranged to reduce dislocation density of the quantum well light-emitting layer for growth and improve lattice quality of the quantum well light-emitting layer. Optionally, the first n_sl layer and the second n_sl layer are sequentially and circularly arranged from bottom to top, and the cycle number is 10-20. Optionally, the silicon doping concentration of the first n_sl layer is between 1×10 18～5×1018/cm-3, the silicon doping concentration of the second n_sl layer is between 1×10 19～3×1019/cm-3, the silicon doping concentration of the first n_bulk layer is between 1×10 19～3×1019/cm-3, and the silicon doping concentration of the second n_bulk layer is between 5×10 18～1×1019/cm-3. Optionally, the thickness of the first N_SL layer is 15-20 nm, the thickness of the second N_SL layer is 30-35 nm, and the thickness of the N_SL layer is 450-550 nm. Optionally, the thickness of the first N_bulk layer is 500-600 nm, the thickness of the second N_bulk layer is 500-600 nm, and the thickness of the N_bulk layer is 1000-1200 nm. Optionally, the qua