CN-114826154-B - Circuit arrangement and oscillator

CN114826154BCN 114826154 BCN114826154 BCN 114826154BCN-114826154-B

Abstract

The invention provides a circuit device and an oscillator, which can improve the linearity of the capacitance value of a variable capacitance circuit for controlling the oscillation frequency. The circuit arrangement comprises a processing circuit and an oscillating circuit for generating capacitance control data. The oscillation circuit has a variable capacitance circuit whose capacitance value is variably controlled in accordance with capacitance control data, and an oscillation frequency of the oscillation circuit is controlled by the capacitance value of the variable capacitance circuit. The variable capacitance circuit has an array of capacitors. The capacitor array has a plurality of capacitors, the capacitance values of each of which are binary weighted, and a plurality of switches, which are controlled to be turned on and off according to capacitance control data. The processing circuit outputs capacitance control data obtained by performing dithering processing so that the capacitance value of the variable capacitance circuit is switched to the 1 st capacitance value and the 2 nd capacitance value in a time-division manner.

Inventors

TORIUMI YUICHI
HANEDA HIDEO
Gutter mouth wise man is flat
TANAKA ATSUTSUGU

Assignees

精工爱普生株式会社
精工爱普生株式会社

Dates

Publication Date: 20260421
Application Date: 20220127
Priority Date: 20210129

Claims (9)

1. A circuit arrangement, characterized in that, the circuit device includes: A processing circuit that generates capacitance control data; an oscillation circuit having a variable capacitance circuit whose capacitance value is variably controlled in accordance with the capacitance control data, an oscillation frequency of the oscillation circuit being controlled by the capacitance value of the variable capacitance circuit, The variable capacitance circuit has an array of capacitors, The capacitor array has: A plurality of capacitors, the capacitance value of each of the plurality of capacitors being weighted binary, and A plurality of switches which are arranged in series with the plurality of capacitors between an oscillation node and a ground node of the oscillation circuit and are controlled to be turned on and off according to the capacitance control data, The processing circuit outputs the capacitance control data subjected to the dithering processing in such a manner that the capacitance value of the variable capacitance circuit is switched to the 1 st capacitance value and the 2 nd capacitance value in time division, The processing circuit has: a temperature compensation unit that performs temperature compensation processing based on temperature detection data, and outputs the result of the temperature compensation processing as input capacitance control data; a dithering processing unit for performing the dithering process on the input capacitance control data and outputting the capacitance control data after the dithering process, and A time division processing unit that performs time division processing on the post-dither capacitance control data, The dither processing unit samples the input capacitance control data at predetermined intervals in the dither processing, In the 1 st period of the predetermined interval, switching the input capacitance control data of the 1 st period, which is the 1 st post-dither-processing capacitance control data corresponding to the 1 st capacitance value, and the data obtained by adding 1 LSB to the input capacitance control data of the 1 st period, which is the 2 nd post-dither-processing capacitance control data corresponding to the 2 nd capacitance value, in a time-division manner, In a 2 nd period after the 1 st period, time-divisionally switching the input capacitance control data of the 2 nd period as the 1 st post-dither-processing capacitance control data and data obtained by adding 1 LSB to the input capacitance control data of the 2 nd period as the 2 nd post-dither-processing capacitance control data, The time division processing unit performs the time division processing so that the capacitance value of the variable capacitance circuit becomes the 1 st capacitance value on time average based on the 1 st post-dither-processing capacitance control data, and outputs the capacitance control data so that the capacitance value of the variable capacitance circuit becomes the 2 nd capacitance value on time average based on the 2 nd post-dither-processing capacitance control data.
2. The circuit arrangement of claim 1, wherein, The plurality of capacitors of the capacitor array have: A1 st capacitor group formed by connecting a plurality of MIM capacitors in parallel and corresponding to high-order side bits of the capacitance control data, and And a 2 nd capacitor group formed by connecting a plurality of MIM capacitors in series, wherein the 2 nd capacitor group corresponds to the low-order side bit of the capacitance control data.
3. The circuit arrangement of claim 1, wherein, The time division processing part When the 1 st post-dither capacitance control data is input, the capacitance control data corresponding to a 3 rd capacitance value equal to or smaller than the 1 st capacitance value and the capacitance control data corresponding to a 4 th capacitance value larger than the 1 st capacitance value are output to the variable capacitance circuit in a time-division manner so that the capacitance value of the variable capacitance circuit becomes the 1 st capacitance value on a time-average, When the 2 nd post-dither-processing capacitance control data is input, the capacitance control data corresponding to a 5 th capacitance value equal to or smaller than the 2 nd capacitance value and the capacitance control data corresponding to a 6 th capacitance value larger than the 2 nd capacitance value are output to the variable capacitance circuit in a time-division manner so that the capacitance value of the variable capacitance circuit becomes the 2 nd capacitance value on a time-average.
4. A circuit arrangement according to claim 3, characterized in that, The capacitor array has: a switching capacitor having a capacitance value identical to a smallest capacitance value of the plurality of binary-weighted capacitors, and A switching switch provided in series with the switching capacitor between the oscillation node and the ground node, The switch for switching is turned off when the capacitance control data corresponding to the 3 rd capacitance value is input, turned on when the capacitance control data corresponding to the 4 th capacitance value is input, turned off when the capacitance control data corresponding to the 5 th capacitance value is input, and turned on when the capacitance control data corresponding to the 6 th capacitance value is input.
5. A circuit arrangement, characterized in that, the circuit device includes: A processing circuit that generates capacitance control data; an oscillation circuit having a variable capacitance circuit whose capacitance value is variably controlled in accordance with the capacitance control data, an oscillation frequency of the oscillation circuit being controlled by the capacitance value of the variable capacitance circuit, The variable capacitance circuit has an array of capacitors, The capacitor array has: A plurality of capacitors, the capacitance value of each of the plurality of capacitors being weighted binary, and A plurality of switches which are arranged in series with the plurality of capacitors between an oscillation node and a ground node of the oscillation circuit and are controlled to be turned on and off according to the capacitance control data, The processing circuit outputs the capacitance control data subjected to the dithering processing in such a manner that the capacitance value of the variable capacitance circuit is switched to the 1 st capacitance value and the 2 nd capacitance value in time division, The processing circuit samples input capacitance control data at predetermined intervals in the dithering process, and time-switches the input capacitance control data sampled in accordance with each period to the input capacitance control data sampled in accordance with each period and the data obtained by adding 1 LSB to the input capacitance control data sampled in accordance with each period in each period divided at the predetermined intervals in a period shorter than the predetermined intervals.
6. The circuit arrangement of claim 5, wherein, The processing circuit has: A temperature compensation unit for performing a temperature compensation process based on temperature detection data and outputting the result of the temperature compensation process as the input capacitance control data, and And a dithering processing unit configured to perform the dithering process on the input capacitance control data and output the capacitance control data after the dithering process.
7. The circuit arrangement of claim 6, wherein, The processing circuit outputs the post-dither capacitance control data to the variable capacitance circuit as the capacitance control data.
8. The circuit arrangement of claim 6, wherein, The processing circuit has a time division processing section for performing time division processing on the post-dither capacitance control data, The dithering processing section outputs, time-divisionally, 1 st dithering-processed capacitance control data corresponding to the 1 st capacitance value and 2 nd dithering-processed capacitance control data corresponding to the 2 nd capacitance value, The time division processing unit performs the time division processing so that the capacitance value of the variable capacitance circuit becomes the 1 st capacitance value on time average based on the 1 st post-dither-processing capacitance control data, and outputs the capacitance control data so that the capacitance value of the variable capacitance circuit becomes the 2 nd capacitance value on time average based on the 2 nd post-dither-processing capacitance control data.
9. An oscillator, the oscillator comprising: A circuit arrangement as claimed in any one of claims 1 to 8, and And a vibrator that oscillates by being driven by the oscillation circuit.

Description

Circuit arrangement and oscillator Technical Field The present invention relates to a circuit device, an oscillator, and the like. Background A temperature-compensated oscillator is known in which a capacitor array is connected to an oscillation node of an oscillation circuit, and a capacitance value of the capacitor array is controlled according to temperature, thereby performing temperature compensation on an oscillation frequency. The digital temperature compensated oscillator disclosed in patent document 1 has a plurality of 1 st capacitive elements having the same capacitance value as each other and a 2 nd capacitive element having a capacitance value of 1/(n+1) of the capacitance value of the 1 st capacitive element in order to perform precise control using a small number of capacitive elements. The capacitor array is composed of a plurality of 1 st and 2 nd capacitive elements, and the digital temperature compensation oscillator temperature compensates the oscillation frequency by controlling the capacitance value of the capacitor array according to the temperature. Patent document 1 Japanese patent laid-open No. 5-218738 In temperature compensation using a capacitor array, linearity of capacitance values of the capacitor array affects compensation accuracy of the temperature compensation. As the capacitor array, a configuration in which the capacitance values of the respective capacitors are binary weighted is considered. For example, let the capacitance value corresponding to LSB be C, the capacitor array has capacitors of C, 2C, 4C, and 8C. In this case, for example, when switching between the state where c+2c+4c=7c and the state where 8C is selected, or when switching between the state where c+2c=3c and the state where 4C is selected, there is a problem that linearity of the capacitance value tends to be reduced due to the influence of parasitic capacitance, manufacturing variations, or the like. Disclosure of Invention One embodiment of the present invention relates to a circuit device including a processing circuit that generates capacitance control data, an oscillation circuit that has a variable capacitance circuit whose capacitance value is variably controlled in accordance with the capacitance control data, the oscillation frequency of the oscillation circuit being controlled by the capacitance value of the variable capacitance circuit, the variable capacitance circuit having a capacitor array that has a plurality of capacitors whose capacitance values are binary weighted, and a plurality of switches that are provided in series with the plurality of capacitors between an oscillation node and a ground node of the oscillation circuit and are controlled to be turned on and off in accordance with the capacitance control data, the processing circuit outputting the capacitance control data after dither processing in such a manner that the capacitance value of the variable capacitance circuit is switched to a1 st capacitance value and a2 nd capacitance value in time division. Another aspect of the present invention relates to an oscillator including the circuit device described above, and a vibrator that oscillates by being driven by the oscillation circuit. Drawings Fig. 1 is a configuration example of a circuit device and an oscillator. Fig. 2 is a detailed configuration example of the oscillating circuit and the variable capacitance circuit. Fig. 3 shows a 1 st detailed configuration example of the capacitor array. Fig. 4 is a detailed configuration example of the capacitor. Fig. 5 is a detailed configuration example of the capacitor. Fig. 6 is a detailed configuration example of the capacitor. Fig. 7 is a structural example of a basic capacitor constituting a capacitor and a basic switch constituting a switch. Fig. 8 is a capacitance value of the variable capacitance circuit with respect to the capacitance control data in the case where the dither process by the dither processing portion is not performed. Fig. 9 is a timing chart illustrating the operation of the processing circuit. Fig. 10 shows capacitance values of the variable capacitance circuit with respect to capacitance control data when the dithering process according to the present embodiment is applied. Fig. 11 shows a1 st detailed configuration example of the processing circuit and the memory. Fig. 12 is a 2 nd detailed configuration example of the capacitor array. Fig. 13 is a2 nd detailed configuration example of the processing circuit and the memory. Fig. 14 is an example of table 2 stored in the time division pattern storage unit. Fig. 15 is a timing chart illustrating the operation of the processing circuit in the detailed configuration example of fig. 2. Fig. 16 is a capacitance value of the variable capacitance circuit with respect to the capacitance control data in the case where the dither process by the dither processing portion is not performed. Fig. 17 shows capacitance values of the variable capacitance circuit with re