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CN-114884517-B - CRC hardware computing system and chip

CN114884517BCN 114884517 BCN114884517 BCN 114884517BCN-114884517-B

Abstract

The invention discloses a CRC hardware computing system and a chip, wherein the CRC hardware computing system comprises i selection processing arrays, each selection processing array comprises m selection control modules, each bit of information value of an information field is provided with a corresponding selection processing array in the CRC hardware computing system, each power item in the generating polynomial is provided with a corresponding selection control module except for the coefficient of the highest power of the generating polynomial, each selection control module is used for selecting the CRC initial value associated with the exclusive OR result or the corresponding power of the information value of the corresponding bit in the information field according to the coefficient of the corresponding power in the generating polynomial under the triggering of a clock signal, and transmitting the CRC initial value to the associated selection control module except for the selection processing array where the selection control module is located so as to output CRC codes in parallel after a plurality of clock cycles.

Inventors

  • Cheng Xufan

Assignees

  • 珠海一微半导体股份有限公司

Dates

Publication Date
20260505
Application Date
20220421

Claims (18)

  1. 1. The CRC hardware computing system is characterized in that the CRC hardware computing system is used for acquiring configuration information and information fields, determining a generating polynomial according to the configuration information, and providing a clock signal, coefficients of powers in the generating polynomial and the information fields for each selected processing array; The CRC hardware computing system comprises i selection processing arrays, wherein each selection processing array is configured to be controlled by coefficients of corresponding powers except for the highest-power item in the generating polynomial, each selection processing array comprises m selection control modules, each selection control module is used for inputting information values of corresponding bits of the information field, each bit of information value of the information field is provided with the corresponding selection processing array in the CRC hardware computing system, and each power item in the generating polynomial is provided with the corresponding selection control module except for the coefficient of the highest power of the generating polynomial; Each selection control module is used for selecting an exclusive or result of an information value of a corresponding bit in the information field and an associated numerical value or a CRC initial value associated with the corresponding power according to a coefficient of the corresponding power in the generating polynomial under the triggering of a clock signal, and transmitting the result to an associated selection control module except a selection processing array where the selection control module is positioned; wherein, m is configured as the number of bits equal to the initial value of CRC, and m is equal to the number of times of the highest order item in the generating polynomial; Each selection control module is used for selecting an exclusive or result of the corresponding bit information value of the information field and the associated numerical value or a CRC initial value associated with the corresponding power according to the coefficient of the corresponding power in the generating polynomial, transmitting the exclusive or result of the corresponding bit information value of the information field and the associated numerical value or the CRC initial value associated with the corresponding power to the selection control module corresponding to the relatively low bit information value of the information field, and outputting the exclusive or result to the selection control module corresponding to the relatively high power coefficient in the selection control module; The exclusive OR calculating unit of the jth column of the p-th row is used for exclusive-or-ing the CRC initial value corresponding to the highest bit, the CRC initial value corresponding to the (p-1) power and the information value of the (i-j-1) th bit of the information field, outputting the exclusive OR result of the exclusive OR calculating unit of the jth column of the p-th row, and determining the exclusive OR result of the information value of the corresponding bit of the information field and the associated numerical value; the storage unit of the p-th row and the j-th column is used for storing CRC initial values corresponding to the (p-1) power, wherein the CRC initial values corresponding to the (p-1) power are CRC initial values associated with the corresponding power; the p-th row and j-th column selector is used for selecting an exclusive OR result of the p-th row and j-th column exclusive OR calculation unit or a CRC initial value corresponding to the (p-1) power stored in the p-th row and j-th column storage unit to output according to the coefficient of the p-th power in the generator polynomial, and configuring an output result of the p-th row and j-th column selector as an output value of a p-th row and j-th column selection control module, wherein the p-th row and j-th column selection control module comprises the p-th row and j-th column exclusive OR calculation unit, the p-th row and j-th column selector and the p-th row and j-th column storage unit, and the p-th row and j-th column selection control module is positioned in a j-th column selection processing array; The (p+1) th row and (j+1) th column selection control module is used for transmitting the output result of the (p+1) th row and (j+1) th column selector to the (p+1) th row and (j+1) th column storage unit and updating the output result to a CRC initial value corresponding to the power of p under the triggering of the clock signal, wherein the (p+1) th row and (j+1) th column selection control module comprises the (p+1) th row and (j+1) th column XOR calculation unit and the (p+1) th row and (j+1) th column storage unit, and the (p+1) th row and (j+1) th column selection control module is positioned in the (j+1) th column selection processing array; The selection control modules of the p-th row and the j-th column are not all selection control modules corresponding to the coefficient of the higher power, and are not all selection processing arrays corresponding to the information value of the lowest bit of the information field, wherein the p is smaller than m-1, the p is larger than 0, the m is larger than 2, the j is larger than or equal to 0, the j is smaller than i-1, the i is larger than 1, the m, the i and the p are all positive integers, and the j is an integer; The CRC initial value input by the selection control module of the 0 th column is configured before the CRC hardware computing system starts to process the information field, and supports to be updated under the triggering of the clock signal.
  2. 2. The CRC hardware computing system of claim 1, wherein the CRC hardware computing system comprises a product of m and i, and a plurality of selection control modules, wherein all the selection control modules form an m-row and i-column arrangement mode, so that the CRC hardware computing system has i-column selection processing arrays, and each selection processing array has m-row selection control modules; Each selection control module comprises an exclusive-or calculation unit, a storage unit and a selector, so that the exclusive-or calculation unit, the storage unit and the selector are arranged in the CRC hardware calculation system in an m-row i-column arrangement mode.
  3. 3. The CRC hardware calculation system according to claim 2, characterized in that the xor calculation unit of row 0 and column j is configured to xor a CRC initial value corresponding to a highest bit with an information value of a (i-j-1) th bit of the information field, output an xor result of the xor calculation unit of row 0 and column j, and determine an xor result of the information value of a corresponding bit of the information field and an associated value; The storage unit of the 0 th row and the j th column is used for storing a preset constant, wherein the preset constant is the CRC initial value associated with the corresponding power; The selector of the 0 th row and the j th column is used for selecting the exclusive OR result of the exclusive OR calculation unit of the 0 th row and the j th column or the preset constant output stored by the storage unit of the 0 th row and the j th column according to the coefficient of the 0 th power in the generator polynomial, and configuring the output result of the selector of the 0 th row and the j th column as the output value of the selection control module of the 0 th row and the j th column, wherein the selection control module of the 0 th row and the j th column comprises the exclusive OR calculation unit of the 0 th row and the j th column, the selector of the 0 th row and the j th column and the storage unit of the 0 th row and the j th column, and the selection control module of the 0 th row and the j th column is positioned in the selection processing array of the j th column; The selection control module of the 0 th row and the j th column is used for transmitting the output result of the selector of the 0 th row and the j th column to the exclusive OR calculation unit of the 1 st row and the storage unit of the 1 st row and the j+1 th column and updating the output result into the CRC initial value associated with the corresponding power under the triggering of the clock signal, wherein the selection control module of the 1 st row and the j+1 th column comprises the exclusive OR calculation unit of the 1 st row and the (j+1) th column and the storage unit of the 1 st row and the (j+1) th column, and the selection control module of the 0 th row and the (j+1) th column is positioned in the selection processing array of the (j+1) th column; And the selection control modules of the 0 th row and the j th column are not all the selection control modules corresponding to the coefficients of the highest power, and are not positioned in the selection processing array corresponding to the information value of the lowest bit of the information field.
  4. 4. The CRC hardware computing system according to claim 2, characterized in that, among all the selection control modules corresponding to the coefficients of the higher power, each selection control module is configured to select, according to the coefficients of the corresponding power in the generator polynomial, an exclusive or result of the information value of the corresponding bit of the information field and the associated value or a CRC initial value associated with the corresponding power, in addition to the selection control module in the selection processing array corresponding to the information value of the lowest bit of the information field, and transmit to all the selection control modules in the selection processing array corresponding to the information value of the relatively lower bit of the information field.
  5. 5. The CRC hardware calculation system according to claim 4, characterized in that the xor calculation unit of the (m-1) th row and the j-th column is configured to xor a CRC initial value corresponding to a highest bit, a CRC initial value corresponding to a (m-2) th power, and an information value of the (i-j-1) th bit of the information field, output an xor result of the xor calculation unit of the (m-1) th row and the 0 th column, and determine the xor result as an xor result of the information value of the corresponding bit of the information field and an associated value; The (m-1) th row and the (j) th column are used for storing CRC initial values corresponding to the (m-2) th power, wherein the CRC initial values corresponding to the (m-2) th power are CRC initial values associated with the corresponding power; The (m-1) th row and j th column selector is used for selecting an exclusive OR result of an exclusive OR calculation unit of the (m-1) th row and j th column or a CRC initial value corresponding to the (m-2) th power stored in a storage unit of the (m-1) th row and j th column according to the coefficient of the (m-1) th power in the generating polynomial, and configuring an output result of the (m-1) th row and j th column selector as an output value of a selection control module of the (m-1) th row and j th column, wherein the selection control module of the (m-1) th row and j th column comprises the exclusive OR calculation unit of the (m-1) th row and j th column storage unit and the (m-1) th row and j th column selector; the selecting control module of the (m-1) th row and the (j) th column is used for transmitting the output result of the (m-1) th row and the (j) th column to all exclusive-OR calculating units of the (j+1) th column, and updating the output result to be the CRC initial value corresponding to the highest bit required by exclusive-OR of all exclusive-OR calculating units of the (j+1) th column under the triggering of the clock signal, wherein all exclusive-OR calculating units of the (j+1) th column are all selecting control modules in a selecting processing array corresponding to the information value positioned at the relatively low bit of the information field; The j is greater than or equal to 0, j is less than i-1, i is greater than 1, m and i are positive integers, j is an integer, the (m-1) th row and the j-th column select control modules are all select control modules corresponding to the coefficient of the highest power, except select control modules in a select processing array corresponding to the information value of the lowest bit of the information field, and all select control modules corresponding to the coefficient of the highest power are all select control modules corresponding to the coefficient of the highest power of the generator polynomial.
  6. 6. The CRC hardware computing system according to claim 2, characterized in that each selection control module in the selection processing array corresponding to the information value of the lowest order bit of the information field is configured to select, according to the coefficient of the corresponding power in the generator polynomial, an exclusive-or result of the information value of the corresponding bit of the information field and the associated data or a CRC initial value associated with the corresponding power, transmit the result to the selection processing array corresponding to the information value of the highest order bit of the information field, and output the result to the selection control module corresponding to the selection processing array corresponding to the coefficient of the corresponding power.
  7. 7. The CRC hardware calculation system according to claim 6, characterized in that the exclusive-or calculation unit of the p-th row (i-1) column is configured to exclusive-or the CRC initial value corresponding to the most significant bit, the CRC initial value corresponding to the (p-1) power, and the information value of the least significant bit of the information field, and output the exclusive-or result of the exclusive-or calculation unit of the p-th row (i-1) column, to determine as the exclusive-or result of the information value of the corresponding bit of the information field and the associated numerical value; the storage unit of the (i-1) th column of the p-th row is used for storing CRC initial values corresponding to the (p-1) th power, wherein the CRC initial values corresponding to the (p-1) th power are CRC initial values associated with the corresponding power; The selector of the (i-1) th row is used for selecting an exclusive OR result of the exclusive OR calculation unit of the (i-1) th row of the p th row or a CRC initial value corresponding to the (p-1) th power stored in the storage unit of the (i-1) th row of the p th row according to the coefficient of the p power in the generating polynomial, and configuring an output result of the selector of the (i-1) th row of the p th row as an output value of a selection control module of the (i-1) th row of the p th row, wherein the selection control module of the (i-1) th row of the p th row comprises the exclusive OR calculation unit of the (i-1) th row of the p th row, the storage unit of the (i-1) th row of the p th row and the selector of the (i-1) th row of the p th row, and the selection control module of the (i-1) th row of the p is positioned in a selection processing array corresponding to the information value of the lowest bit of the information field; The p-th row (i-1) column selection control module is a selection control module in the selection processing array corresponding to the information value of the lowest bit of the information field except the 0-th row selection control module, wherein p is smaller than or equal to m-1, p is larger than 0, m is larger than 1, i and m are positive integers.
  8. 8. The CRC hardware calculation system according to claim 6, characterized in that the exclusive-or calculation unit of row 0 and column (i-1) is configured to exclusive-or the CRC initial value corresponding to the most significant bit with the information value of the least significant bit of the information field, output the exclusive-or result of the exclusive-or calculation unit of row 0 and column j, and determine the exclusive-or result of the information value of the corresponding bit of the information field and the associated numerical value; the storage unit of the 0 th row and the (i-1) th column is used for storing a preset constant, wherein the preset constant is the CRC initial value associated with the corresponding power; the selector of the 0 th row and the (i-1) th column is used for selecting an exclusive OR result of the exclusive OR calculation unit of the 0 th row and the (i-1) th column or a preset constant output stored by the storage unit of the 0 th row and the (i-1) th column according to the coefficient of the 0 th power in the generating polynomial, and configuring an output result of the selector of the 0 th row and the (i-1) th column as an output value of a selection control module of the 0 th row and the (i-1) th column, wherein the selection control module of the 0 th row and the (i-1) th column comprises the exclusive OR calculation unit of the 0 th row and the (i-1) th column, the selector of the 0 th row and the (i-1) th column and the storage unit of the 0 th row and the (i-1) th column, and the selection control module of the 0 th row and the (i-1) th column is the selection control module of the 0 th row in the selection processing array corresponding to the information value of the lowest bit of the information field.
  9. 9. The CRC hardware computing system of claim 6, wherein each selection control module of column 0 is connected to a corresponding register, wherein a data input of one selection control module is correspondingly connected to a data output of one register, and a data input of each register is connected to a selector of the same row of column (i-1) such that coefficients of the same power are connected by the register between the selection control module corresponding to the selection processing array of column 0 and the selection control module corresponding to the selection processing array of column (i-1), wherein the selection processing array of column 0 is a selection processing array corresponding to an information value of a most significant bit of the information field, and the selection processing array of column (i-1) is a selection processing array corresponding to an information value of a least significant bit of the information field; The clock end of each register is connected with the clock signal, and each register is used for caching the output result of the selector of the (i-1) th column of the same row under the triggering of the clock signal.
  10. 10. The CRC hardware computing system according to any one of claims 2-9, characterized in that the manner of selecting, based on coefficients of corresponding powers in the generator polynomial, an exclusive or result of the information value of the corresponding bit of the information field with the associated value or a CRC initial value associated with the corresponding power comprises: When the coefficient of the corresponding power in the generating polynomial is configured by the CRC hardware computing system to be 1, the gating end of the selector in the corresponding selection control module receives a first level signal, and the selector gates an exclusive-OR computing unit in the selection control module in which the selector is positioned and outputs an exclusive-OR result of the exclusive-OR computing unit, wherein the exclusive-OR result of the information value of the corresponding bit of the information field and the association numerical value is the exclusive-OR result of the exclusive-OR computing unit, and the association numerical value comprises a CRC initial value corresponding to the highest bit and/or a CRC initial value associated with the corresponding power; When the coefficient of the corresponding power in the generating polynomial is configured to be 0 by the CRC hardware computing system, the gating end of the selector in the corresponding selection control module receives a second level signal, and the CRC initial value associated with the corresponding power stored in the storage unit in the selection control module where the selector gates is located is output, wherein the second level signal is different from the first level signal.
  11. 11. The CRC hardware computing system of claim 10, wherein the configuration information includes a CRC type, coefficients of a generator polynomial, and a CRC initial value; The CRC hardware computing system is used for determining a mode of generating a polynomial according to the configuration information, and comprises the following steps: Determining the type of the generating polynomial and coefficients of powers in the generating polynomial according to the CRC type and the coefficients of the generating polynomial; Wherein, the CRC initial value is set and supported to be updated according to a communication protocol followed by the information field before the CRC hardware computing system starts to process the information field; Wherein the CRC initial value corresponding to the highest order bit is the CRC initial value corresponding to the highest order power of the generator polynomial.
  12. 12. The CRC hardware computing system of claim 11, wherein when said CRC type is CRC8, m is set to 8,i to 4, and said information field is comprised of a 4-bit information value.
  13. 13. A chip comprising a CRC hardware computing system as claimed in any one of claims 1 to 12.
  14. 14. The chip of claim 13, wherein the CRC hardware computing system comprises a product of m and i, and a plurality of selection control modules, wherein all the selection control modules form an m-row and i-column arrangement mode, so that the CRC hardware computing system has i-column selection processing arrays, and each selection processing array has m-row selection control modules; Each selection control module comprises an exclusive-or calculation unit, a storage unit and a selector, so that the exclusive-or calculation unit, the storage unit and the selector are arranged in the CRC hardware calculation system in an m-row i-column arrangement mode.
  15. 15. The chip according to claim 13, wherein each of the selection control modules is configured to select, according to the coefficient of the corresponding power in the generator polynomial, an exclusive or result of the information value of the corresponding bit of the information field and the associated value or a CRC initial value associated with the corresponding power, except for all of the selection control modules corresponding to the coefficient of the higher power and the selection control array corresponding to the information value of the lowest bit of the information field, transmit the result to the selection control array corresponding to the information value of the relatively lower bit of the information field, and output the result to the selection control module corresponding to the coefficient of the higher power in the selection control array.
  16. 16. The chip of claim 13, wherein among all the selection control modules corresponding to the coefficients of the higher power, each selection control module is configured to select, according to the coefficients of the corresponding power in the generator polynomial, an exclusive or result of the information value of the corresponding bit of the information field and the associated numerical value or a CRC initial value associated with the corresponding power, and transmit the exclusive or result to all the selection control modules in the selection control array corresponding to the information value of the relatively lower bit of the information field, except for the selection control module in the selection control array corresponding to the information value of the lowest bit of the information field.
  17. 17. The chip of claim 13, wherein each selection control module in the selection processing array corresponding to the information value of the lowest order bit of the information field is configured to select, according to the coefficient of the corresponding power in the generator polynomial, an exclusive or result of the information value of the corresponding bit of the information field associated with the associated data or a CRC initial value associated with the corresponding power, transmit the result to the selection processing array corresponding to the information value of the highest order bit of the information field, and output the result to the selection control module corresponding to the selection processing array corresponding to the coefficient of the corresponding power.
  18. 18. The chip of claim 14, wherein each of the select control modules of column 0 is connected to a corresponding register, wherein the data input of one select control module is correspondingly connected to the data output of one register, and the data input of each register is connected to the selector of column (i-1) of the same row, such that the coefficients of the same power are connected by the register between the select control module corresponding to the select processing array of column 0 and the select control module corresponding to the select processing array of column (i-1), wherein the select processing array of column 0 is the select processing array corresponding to the information value of the most significant bit of the information field, and the select processing array of column (i-1) is the select processing array corresponding to the information value of the least significant bit of the information field; The clock end of each register is connected with the clock signal, and each register is used for caching the output result of the selector of the (i-1) th column of the same row under the triggering of the clock signal.

Description

CRC hardware computing system and chip Technical Field The invention belongs to the technical field of cyclic redundancy check circuits, and particularly relates to a CRC hardware computing system and a chip. Background The cyclic redundancy check (Cyclic Redundancy Check, CRC) is used to check the correctness and integrity of data transmission, and the CRC operation has strong error detection capability and is easy to be implemented by an encoder or a detection circuit, such as a Linear Feedback Shift Register (LFSR), the initial value of the LFSR is called as a seed of a pseudo-random sequence, and the last trigger outputs a periodically repeated pseudo-random sequence. The CRC8 serial shift circuit disclosed by the traditional technology can calculate a CRC check code in a shift mode, and the corresponding determined generation polynomial is G=g 8X8+g7X7+...+g1X1 +1. The conventional technology has at least the following problems that in a CRC circuit, each time multi-bit information code value is processed in parallel, a longer clock period is required to be consumed, and an exclusive OR gate and a multiplier are correspondingly configured for each bit of information code value to be processed in one clock period, so that more time is required to configure and process coefficients of each power of the generator polynomial, and multiplication operation is required to be performed for each coefficient and an associated information code, so that CRC checking time is longer and hardware resource cost is overlarge. Disclosure of Invention In order to overcome the technical defects, the invention discloses a CRC hardware computing system and a chip, and the specific technical scheme is as follows: A CRC hardware computing system is used for acquiring configuration information and information fields, then providing a clock signal to each selection processing array, coefficients and information fields of powers in the generation polynomial according to a generation polynomial determined by the configuration information, wherein the CRC hardware computing system comprises i selection processing arrays, each selection processing array is configured to be controlled by the coefficients of the corresponding powers except for the highest power item in the generation polynomial, each selection processing array comprises m selection control modules, each selection control module is used for inputting information values of corresponding bits of the information fields, each bit information value of the information fields is provided with a corresponding selection processing array in the CRC hardware computing system, each power item is provided with a corresponding selection control module in each selection processing array except for the coefficient of the highest power of the generation polynomial, each selection control module is triggered by the clock signal according to the coefficients of the corresponding powers in the generation polynomial, the corresponding bits in the selection processing arrays are equal to the CRC information fields, the CRC information of the corresponding to the corresponding powers in the generation polynomial is transmitted to the binary sequence, the CRC information fields are associated with the corresponding values in the binary sequences, and the CRC information fields are calculated according to the values of the corresponding bits in the generation polynomial, and the CRC information fields are equal to the corresponding to the binary sequences, the CRC information is calculated in the binary sequences, and the CRC information is stored in the binary sequences is stored in the CRC hardware system, and has the CRC hardware is a high in the system is a high system. Further, the CRC hardware computing system comprises a product of m and i, all the selection control modules form an m-row and i-column arrangement mode, so that the CRC hardware computing system is provided with i-column selection processing arrays, each selection processing array is provided with m-row selection control modules, each selection control module comprises an exclusive OR computing unit, a storage unit and a selector, and the exclusive OR computing unit, the storage unit and the selector are arranged in the CRC hardware computing system in the m-row and i-column arrangement mode. Further, each selection control module is configured to select, according to the coefficient of the corresponding power in the generator polynomial, an exclusive or result of the information value of the corresponding bit of the information field and the associated value or a CRC initial value associated with the corresponding power, except for all selection control modules corresponding to the coefficient of the higher power and a selection processing array corresponding to the information value of the lowest bit of the information field, transmit the result to the selection processing array corresponding to the information value of