CN-114912604-B - Photon computing system and method for optically performing matrix vector multiplication

CN114912604BCN 114912604 BCN114912604 BCN 114912604BCN-114912604-B

Abstract

Aspects relate to a photonic computing system and a method of optically performing matrix vector multiplication. A photonic computing system includes a light source configured to generate a plurality of input optical signals having mutually different wavelengths, a plurality of optical encoders configured to encode the plurality of input optical signals using respective input values, a first Wavelength Division Multiplexer (WDM) configured to spatially combine the encoded plurality of input optical signals into an input waveguide, a photonic multiplier coupled to the input waveguide and configured to generate a plurality of output optical signals, each output optical signal encoded with a respective output value, the output values representing a product of the respective input values and a common weight value, and a second WDM coupled to the photonic multiplier and configured to spatially separate the plurality of output optical signals.

Inventors

N c harris
D. Bunandar
C. LAMY

Assignees

轻物质公司

Dates

Publication Date: 20260508
Application Date: 20190514
Priority Date: 20180515

Claims (6)

1. A photon processing system, comprising: An optical encoder configured to encode an input vector into a first plurality of optical signals; a light source is arranged in the light source, the photon processor is configured to: Receiving the first plurality of optical signals, each of the first plurality of signals received by a respective input spatial mode of a plurality of input spatial modes of the photon processor; performing a plurality of operations on the first plurality of optical signals, the plurality of operations effecting a matrix multiplication of the input vector with a matrix, and Outputting a second plurality of optical signals representing output vectors, each of the second plurality of signals being transmitted by a respective output spatial mode of a plurality of output spatial modes of the photon processor; an optical receiver configured to detect the second plurality of optical signals and output an electrical digital representation of the output vector, A plurality of front ends, wherein each of the plurality of front ends is associated with one of the plurality of input spatial modes of the photonic processor, wherein each of the plurality of front ends comprises: a plurality of optical encoders, each configured to encode a respective component of the input vector into an optical signal, wherein each optical encoder is configured to output an optical signal having a wavelength different from that output by the other optical encoders, and An input wavelength division multiplexer configured to receive each of the optical signals from each of the plurality of optical encoders in a separate spatial mode and output each of the optical signals in a single spatial mode connected to a corresponding one of the plurality of input spatial modes of the photonic processor, and A plurality of back ends, wherein each of the plurality of back ends is associated with one of the plurality of output spatial modes of the photon processor, wherein each of the plurality of back ends comprises: an output wavelength division multiplexer configured to receive optical signals of different wavelengths from a respective one of the plurality of output spatial modes of the photonic processor and to output each of the optical signals of different wavelengths in a respective one of the plurality of output spatial modes of the wavelength division multiplexer, and A plurality of optical receivers, each configured to determine a respective component of an output vector by detecting a respective optical signal associated with a respective output spatial mode of the wavelength division multiplexer.
2. The photon processing system according to claim 1, wherein the photon processor comprises: a first interconnected variable beam splitter array comprising a first plurality of optical inputs and a first plurality of optical outputs corresponding to the first plurality of input spatial modes; A second interconnected variable beam splitter array comprising a second plurality of optical inputs and a second plurality of optical outputs corresponding to the plurality of output spatial modes, and A plurality of controllable optical elements, each controllable optical element of the plurality of controllable optical elements coupling one light output of the first plurality of light outputs of the first array to a respective one of the second plurality of light inputs of the second array.
3. The photon processing system according to claim 2, further comprising a controller configured to: performing singular value decomposition on the matrix to determine a first singular value decomposition matrix, a second singular value decomposition matrix, and a third singular value decomposition matrix; controlling the first plurality of interconnected variable beamsplitters to implement the first singular value decomposition matrix; Controlling the second plurality of interconnected variable beam splitters to implement the second singular value decomposition matrix, and Controlling the plurality of controllable optical elements to implement the third singular value decomposition matrix, wherein the third singular value decomposition matrix is a diagonal matrix.
4. The photon processing system according to claim 3, wherein the controller further comprises at least one digital-to-analog converter to adjust one or more parameters of the first plurality of interconnected variable splitters and the second plurality of interconnected variable splitters.
5. The photon processing system according to claim 4, wherein: Each variable splitter of the first plurality of interconnected variable splitters and each variable splitter of the second plurality of interconnected variable splitters being associated with a respective address, and The at least one digital-to-analog converter includes a single digital-to-analog converter that uses the address to control a plurality of the first plurality of interconnected variable splitters and/or the second plurality of interconnected variable splitters.
6. The photon processing system of claim 1, wherein the optical receiver comprises a low pass filter configured to perform analog summation of a plurality of subsequent signals associated with each of the plurality of output spatial modes of the photon processor.

Description

Photon computing system and method for optically performing matrix vector multiplication The application is a divisional application of a China national stage patent application with International application number of PCT/US 2019/03181, international application date of 2019, 05 month 14, and the application name of photon processing system and method after entering China national stage on day 12 of 2021, wherein the application number of the divisional application is 201980046744.8. Cross Reference to Related Applications The present application claims priority to U.S. patent application serial No. 62/671,793, entitled "ALGORITHMS FOR TRAINING NEURAL NETWORKS WITH PHOTONIC HARDWARE ACCELERATORS," filed 5/15/2018, attorney docket No. L0858.70001US00, which is incorporated herein by reference in its entirety, in accordance with 35u.s.c. ≡119 (e). The present application is also based on 35U.S. c. ≡119 (e) claiming priority from U.S. provisional patent application serial No. 62/680,557 entitled "PHOTONICS PROCESSING SYSTEMS AND METHODS," filed on 4/6/2018, attorney docket No. L0858.70000US00, which is incorporated herein by reference in its entirety. The present application is also based on 35U.S. c. ≡119 (e) claiming priority from U.S. provisional patent application serial No. 62/689,022, entitled "CONVOLUTIONAL LAYERS FOR NEURAL NETWORKS USING PROGRAMMABLE NANOPHOTONICS," filed on 6/22, 2018, attorney docket No. L0858.70003US00, incorporated herein by reference in its entirety. The present application is also based on 35U.S. c. ≡119 (e) claiming priority from U.S. provisional patent application serial No. 62/755,402 entitled "REAL-NUMBER PHOTONIC ENCODING," filed 11/2018, attorney docket No. L0858.70008US00, which is incorporated herein by reference in its entirety. The present application is also based on 35U.S. c. ≡119 (e) claiming priority from U.S. provisional patent application serial No. 62/792,720 entitled "HIGH-EFFICIENCY DOUBLE-SLOT WAVEGUIDE NANO-OPTOELECTROMECHANICAL PHASE MODULATOR," filed on 1 month 15 in 2019, attorney docket No. L0858.70006US00, which is incorporated herein by reference in its entirety. The present application is also based on 35U.S. c. ≡119 (e) claiming priority from U.S. provisional patent application serial No. 62/793,327 entitled "DIFFERENTIAL, LOW-NOISE HOMODYNE RECEIVER," filed on 1 month 16 in 2019, attorney docket No. L0858.70004US00, which is incorporated herein by reference in its entirety. The present application is also based on 35U.S. c. ≡119 (e) claiming priority from U.S. provisional patent application serial No. 62/834,743, entitled "STABILIZING LOCAL OSCILLATOR PHASES IN A PHOTOCORE", filed on 4/16 in 2019, attorney docket No. L0858.70014US00, incorporated herein by reference in its entirety. Background Processors used in conventional computing include circuitry consisting of millions of transistors to implement logic gates on information bits represented by electrical signals. The architecture of a conventional Central Processing Unit (CPU) is designed for general purpose computing and is not optimized for a particular type of algorithm. Some examples of the types of algorithms that are computationally intensive and cannot be efficiently executed using a CPU include graphics processing, artificial intelligence, neural networks, and deep learning. Thus, specialized processors have been developed with architectures more suited to the particular algorithm. For example, graphics Processing Units (GPUs) have a highly parallel architecture, which makes them more efficient than CPUs for performing image processing and graphics operations. After GPUs are developed for graphics processing, GPUs have also been found to be more efficient than GPUs for other memory-intensive algorithms such as neural networks and deep learning. The increasing popularity of this awareness, artificial intelligence and deep learning has prompted further research into new circuit configurations that can further increase the speed of these algorithms. Disclosure of Invention In some embodiments, a photonic computing system is provided. The photonic computing system may include a photonic computing system that includes a light source configured to generate a plurality of input optical signals having mutually different wavelengths, a plurality of optical encoders configured to encode the plurality of input optical signals using respective input values, a first Wavelength Division Multiplexer (WDM) configured to spatially combine the encoded plurality of input optical signals into an input waveguide, a photonic multiplier coupled to the input waveguide and configured to generate a plurality of output optical signals, each output optical signal encoded with a respective output value, the output values representing a product of the respective input value and a common weight value, and a second WDM coupled to the photonic multiplier and configured to spatially separate the plurality of output opt