CN-114916241-B - Display substrate and display device thereof

Abstract

The present disclosure relates to a display substrate including a display region and a peripheral region surrounding the display region, the peripheral region including a first wiring region including a first sub-wiring region disposed in a first direction away from the display region, a first conductive layer on the substrate, a first dielectric layer on the first conductive layer, a second conductive layer on the first dielectric layer, a second dielectric layer on the second conductive layer, a third conductive layer on the second dielectric layer, a third dielectric layer as a planarization layer on the third conductive layer, and a fourth conductive layer on the third dielectric layer. The fourth wiring is electrically connected to the third wiring. The orthographic projection of the fourth wiring on the substrate at least partially overlaps with the orthographic projection of the third wiring on the substrate.

Inventors

• PANG YUQIAN
• WANG MIAO
• XIAO YUNSHENG

Assignees

• 京东方科技集团股份有限公司
• 京东方科技集团股份有限公司
• 成都京东方光电科技有限公司
• 成都京东方光电科技有限公司

Dates

Publication Date

20260421

Application Date

20201209

Priority Date

20201209

Claims (20)

1. 1. A display substrate, comprising: A substrate including a display region and a peripheral region surrounding the display region, the peripheral region including a first wiring region including a first sub-wiring region disposed in a first direction away from the display region; a first conductive layer on the substrate, the first conductive layer including a first portion in the peripheral region, the first portion of the first conductive layer including a first wire in the first wire region; a first dielectric layer on the first conductive layer; A second conductive layer on the first dielectric layer, the second conductive layer including a first portion on the peripheral region, wherein the first portion of the second conductive layer includes a second wiring in the first wiring region, the first wiring and the second wiring being spaced apart from each other in a direction parallel to the substrate; A second dielectric layer on the second conductive layer; A third conductive layer on the second dielectric layer, the third conductive layer including a first portion in the peripheral region, wherein the first portion of the third conductive layer includes a third wire in the first wire region; a third dielectric layer as a planarization layer on the third conductive layer; A fourth conductive layer on the third dielectric layer, the fourth conductive layer including a first portion on the peripheral region, the first portion of the fourth conductive layer including a fourth wire in the first sub-wire zone, Wherein the fourth wiring is electrically connected to the third wiring, an orthographic projection of the fourth wiring on the substrate and an orthographic projection of the third wiring on the substrate overlap at least partially, Wherein the third dielectric layer includes a first via hole in the first sub-wiring region exposing the third wiring, the fourth wiring is connected to the third wiring via the first via hole, and The first via includes a first array of first sub-vias and a second array of second sub-vias, the first sub-vias and the second sub-vias being configured such that at least one of the first sub-vias is surrounded by the second sub-via nearest to the first sub-via, and at least one of the second sub-vias is surrounded by the first sub-via nearest to the second sub-via.
2. 2. The display substrate according to claim 1, wherein the third wiring and the fourth wiring constitute a first power supply signal line.
3. 3. The display substrate of claim 1, wherein at least one of the first sub-vias is located at a center of a shape surrounded by the second sub-via that is nearest to the first sub-via, and at least one of the second sub-vias is located at a center of a shape surrounded by the first sub-via that is nearest to the second sub-via.
4. 4. A display substrate according to any of claims 1-3, wherein the cross-sectional shape of the first via along a plane parallel to the substrate comprises a truncated square.
5. 5. The display substrate according to claim 4, wherein the truncated square has a side length of 11 μm.
6. 6. The display substrate of claim 1, wherein the first portion of the fourth conductive layer comprises a second via exposing the third dielectric layer.
7. 7. The display substrate of claim 6, wherein the second via comprises a first array of third sub-vias and a second array of fourth sub-vias, the third sub-vias and the fourth sub-vias configured such that at least one of the third sub-vias is surrounded by the fourth sub-via that is nearest to the third sub-via, and at least one of the fourth sub-vias is surrounded by the third sub-via that is nearest to the fourth sub-via.
8. 8. The display substrate of claim 7, wherein at least one of the third sub-vias is located at a center of a shape surrounded by the fourth sub-via that is nearest to the third sub-via, and at least one of the fourth sub-vias is located at a center of a shape surrounded by the third sub-via that is nearest to the fourth sub-via.
9. 9. The display substrate of any of claims 6-8, wherein a cross-sectional shape of the second via along a plane parallel to the substrate comprises a square.
10. 10. The display substrate according to claim 9, wherein a side length of the square is 16 μm.
11. 11. The display substrate of claim 6, wherein at least one of the first vias is located at a center of a shape surrounded by the second via that is nearest to the first via, and at least one of the second vias is located at a center of a shape surrounded by the first via that is nearest to the second via.
12. 12. The display substrate of claim 11, wherein a spacing between the first via and the second via in the first direction is 6.5 μm, In a second direction parallel to the substrate and perpendicular to the first direction, a spacing between the first via and the second via is 16.5 μm.
13. 13. The display substrate according to claim 1, further comprising a thin film transistor in the display region, the thin film transistor including an active layer on the substrate, a gate insulating layer on the active layer, and a gate electrode on the gate insulating layer, Wherein said first conductive layer further comprises a second portion located in said display region, said second portion of said first conductive layer comprising said gate electrode of said thin film transistor, The third conductive layer further includes a second portion located in the display region, the second portion of the third conductive layer including a source/drain electrode of the thin film transistor, the source/drain electrode being connected to a source/drain region of the active layer through the first dielectric layer, the second dielectric layer, and the gate insulating layer.
14. 14. The display substrate of claim 13, wherein the fourth conductive layer further comprises a second portion located in the display region, the second portion of the fourth conductive layer being connected to the source/drain electrode of the thin film transistor through the third dielectric layer.
15. 15. The display substrate of claim 14, further comprising a fourth dielectric layer as a planarizing layer on the fourth conductive layer, and And the packaging layer is positioned on the fourth dielectric layer.
16. 16. The display substrate of claim 15, further comprising a light emitting device in the display region between the fourth dielectric layer and the encapsulation layer, the light emitting device comprising an anode, a light emitting layer, and a cathode disposed in sequence in a direction perpendicular to the substrate, wherein the anode is between the fourth dielectric layer and the encapsulation layer, the anode is connected to the second portion of the fourth conductive layer via a via in the fourth dielectric layer, The display substrate further includes a pixel defining layer defining a light emitting region between the fourth dielectric layer and the encapsulation layer, the pixel defining layer having an opening exposing the anode.
17. 17. The display substrate of claim 16, wherein the first wiring region further comprises a second sub-wiring region located at a side of the first sub-wiring region remote from the display region, Wherein the display substrate further comprises a dam in the second sub-wiring region, the dam comprising a first dam portion and a second dam portion sequentially spaced apart in a direction away from the display region, Wherein the first dam portion includes the fourth dielectric layer and the pixel definition layer, The second dam portion includes the third dielectric layer, the fourth dielectric layer, and the pixel definition layer.
18. 18. The display substrate according to claim 16 or 17, wherein the peripheral region further comprises a bending region and a second wiring region sequentially disposed in the first direction away from the display region on a side of the first wiring region away from the display region, The bending region has an opening exposing the substrate through the gate insulating layer, the first dielectric layer and the second dielectric layer, and a planarization layer covering the opening, the planarization layer including at least one of the third dielectric layer and the fourth dielectric layer, The second wiring region comprises the gate insulating layer, the first dielectric layer, the second dielectric layer, the third conductive layer, the fourth conductive layer and the fourth dielectric layer which are arranged on the substrate in sequence along the direction perpendicular to the substrate.
19. 19. The display substrate according to claim 2, further comprising a second power signal line which is located in the peripheral region and surrounds the display region and the first power signal line, The second power signal line includes at least one of a portion of the third conductive layer located in the peripheral region and a portion of the fourth conductive layer located in the peripheral region, Wherein the first power signal line is configured to provide a first voltage and the second power signal line is configured to provide a second voltage, the first voltage being higher than the second voltage.
20. 20. The display substrate of claim 1, further comprising a passivation layer between the third conductive layer and the third dielectric layer.

Description

Display substrate and display device thereof Technical Field The embodiment of the disclosure relates to the technical field of display, in particular to a display substrate and a display device thereof. Background In recent years, with further development of technology and industry, organic LIGHT EMITTING Diode (OLED) display panels have been widely used in products such as mobile phones, wearable devices, computers, and the like. BRIEF SUMMARY OF THE PRESENT DISCLOSURE Embodiments of the present disclosure provide a display substrate. The display substrate comprises a substrate, a substrate and a first conducting layer, wherein the substrate comprises a display area and a peripheral area surrounding the display area, the peripheral area comprises a first wiring area, the first wiring area comprises a first sub-wiring area arranged in a first direction far away from the display area, the first conducting layer is arranged on the substrate and comprises a first part arranged on the peripheral area, the first part of the first conducting layer comprises a first wiring in the first wiring area, a first medium layer arranged on the first conducting layer, a second conducting layer arranged on the first medium layer and comprises a first part arranged on the peripheral area, the first part of the second conducting layer comprises a second wiring in the first wiring area, the first wiring and the second wiring are arranged at intervals along a direction parallel to the substrate, the second conducting layer is arranged on the second conducting layer and comprises a second medium layer arranged on the second conducting layer, the third medium layer is arranged on the second conducting layer and comprises a third conducting layer arranged on the third conducting layer and comprises a fourth conducting layer arranged on the third conducting layer, the third conducting layer is arranged on the fourth conducting layer is arranged on the peripheral area, and the third conducting layer comprises a third conducting layer arranged on the third conducting layer is arranged on the fourth conducting layer. The fourth wiring is electrically connected to the third wiring. An orthographic projection of the fourth wiring on the substrate at least partially overlaps an orthographic projection of the third wiring on the substrate. In an embodiment of the present disclosure, the third dielectric layer includes a first via in the first sub-wiring region exposing the third wiring. The fourth wiring is connected to the third wiring via the first via. In an embodiment of the present disclosure, the third wiring and the fourth wiring constitute a first power supply signal line. In an embodiment of the present disclosure, the first via includes a first array of first sub-vias and a second array of second sub-vias. The first sub-via and the second sub-via are configured such that at least one of the first sub-via is surrounded by the second sub-via that is nearest to the first sub-via and at least one of the second sub-via is surrounded by the first sub-via that is nearest to the second sub-via. In an embodiment of the present disclosure, at least one of the first sub-vias is located at a center of a shape surrounded by the second sub-via that is nearest to the first sub-via. At least one second sub-via is located at the center of the shape surrounded by the first sub-via nearest to the second sub-via. In an embodiment of the present disclosure, a cross-sectional shape of the first via along a plane parallel to the substrate includes a truncated square. In an embodiment of the present disclosure, the truncated square has a side length of 11 μm. In an embodiment of the present disclosure, the first portion of the fourth conductive layer includes a second via exposing the third dielectric layer. In an embodiment of the present disclosure, the second via includes a first array of third sub-vias and a second array of fourth sub-vias. The third sub-via and the fourth sub-via are configured such that at least one of the third sub-via is surrounded by the fourth sub-via nearest to the third sub-via and at least one of the fourth sub-via is surrounded by the third sub-via nearest to the fourth sub-via. In an embodiment of the present disclosure, at least one of the third sub-vias is located at a center of a shape surrounded by the fourth sub-via that is nearest to the third sub-via. At least one of the fourth sub-vias is located in the center of the shape surrounded by the third sub-via nearest to the fourth sub-via. In an embodiment of the present disclosure, a cross-sectional shape of the second via along a plane parallel to the substrate comprises a square. In an embodiment of the present disclosure, the sides of the square are 16 μm long. In an embodiment of the disclosure, each of the first vias is located at a center of a shape surrounded by the second via nearest to the first via. Each second via hole is located at the center of a shape s