CN-114924996-B - System and method for addressing a cache with a split index

Abstract

Cache memory mapping techniques are presented. A cache may contain index configuration registers. The registers may configure the locations of the upper and lower index portions of the memory address. The portions may be combined to create a combined index. Among other applications, a configurable split index addressing structure may be used to reduce the rate of cache conflicts that occur between multiple processors decoding video frames in parallel.

Inventors

• R. Richmond

Assignees

• 莫维迪乌斯有限公司

Dates

Publication Date

20260508

Application Date

20160511

Priority Date

20150519

Claims (20)

1. 1. A processor subsystem, comprising: one or more of the processor cores may be configured to, the one or more processor cores are to communicate with a memory; and A cache comprising a plurality of cache lines, the cache to: determining a first index of a first set of bits from a first address associated with a first location of the memory; determining a second index from a second set of bits of the first address separated from the first set of bits of the first address by a third set of bits of the first address, and Data from the first location of the memory is stored into a first cache line of the cache lines referenced by a combined index, the combined index being based on a combination of the first index and the second index.
2. 2. The processor subsystem of claim 1, wherein the cache is to concatenate the first index and the second index to determine an index of the combination.
3. 3. The processor subsystem of claim 1 or 2, wherein the cache is further to combine the third set of bits of the first address and a fourth set of bits of the first address to determine an identifier to identify the first location of the memory.
4. 4. The processor subsystem of claim 3, wherein the cache is to concatenate the third set of bits of the first address and the fourth set of bits of the first address to determine the identifier.
5. 5. The processor subsystem of claim 3, wherein the cache is to determine a location in the first cache line of the cache lines to which the first location of the memory is mapped, the cache is to determine the location based on a fifth set of bits of the first address.
6. 6. The processor subsystem of claim 1 or 2, wherein at least one of the first set of bits of the first address, the second set of bits of the first address, or the third set of bits of the first address has a size of one bit.
7. 7. The processor subsystem of claim 1 or 2, wherein the one or more processor cores comprise at least two processor cores, and respective ones of the at least two processor cores are to access different ones of the cache lines simultaneously.
8. 8. An apparatus, comprising: A cache line referenced by the index; Means for determining a first index portion and a second index portion from respective first and second sets of bits of a first address associated with a first location of a memory, the first and second sets of bits of the first address being separated by a third set of bits of the first address, and Means for mapping the first location of the memory to a first cache line of the cache lines referenced by a first index of the index, the means for mapping to determine the first index of the indexes based on a combination of the first index portion and the second index portion, the cache to store data from the first location of the memory into the first cache line of the cache lines.
9. 9. The apparatus of claim 8, wherein the means for mapping is to concatenate the first index portion and the second index portion to determine the first one of the indexes.
10. 10. The apparatus of claim 8 or 9, wherein the means for determining is to combine the third set of bits of the first address and a fourth set of bits of the first address to determine an identifier to identify the first location of the memory.
11. 11. The apparatus of claim 10, wherein the means for determining is to concatenate the third set of bits of the first address and the fourth set of bits of the first address to determine the identifier.
12. 12. The apparatus of claim 10, wherein the means for determining is to determine a location in the first cache line of the cache line to which the first location of the memory is mapped, the location to be determined based on a fifth set of bits of the first address.
13. 13. The apparatus of claim 8 or 9, wherein at least one of the first set of bits of the first address, the second set of bits of the first address, or the third set of bits of the first address has a size of one bit.
14. 14. The apparatus of claim 8 or 9, further comprising means for scheduling at least two processor cores to access different ones of the cache lines simultaneously.
15. 15. A method, comprising: determining, with logic circuitry, a first index of a first set of bits from a first address associated with a first location of a memory; Determining a second index from a second set of bits of the first address separated from the first set of bits of the first address by a third set of bits of the first address with logic circuitry, and Data from the first location of the memory is stored into a first cache line of a plurality of cache lines referenced by a combined index, the combined index being based on a combination of the first index and the second index.
16. 16. The method of claim 15, further comprising concatenating the first index and the second index to determine an index of the combination.
17. 17. The method of claim 15 or 16, further comprising combining the third set of bits of the first address and a fourth set of bits of the first address to determine an identifier to identify the first location of the memory.
18. 18. The method of claim 17, wherein combining the third set of bits of the first address and the fourth set of bits of the first address comprises concatenating the third set of bits of the first address and the fourth set of bits of the first address to determine the identifier.
19. 19. The method of claim 17, further comprising determining a location in the first cache line of the cache lines to which the first location of the memory is mapped, the location being determined based on a fifth set of bits of the first address.
20. 20. The method of claim 15 or 16, wherein at least one of the first set of bits of the first address, the second set of bits of the first address, or the third set of bits of the first address has a size of one bit.

Description

System and method for addressing a cache with a split index The application is a split application with the title 201680028652.3 for a system and method for addressing caches with split indexes. Cross-reference to related patent applications The present application claims priority from U.S. patent application Ser. No.14/716,588, filed 5/19/2015, and entitled "SYSTEMS AND METHODS FOR ADDRESSING A CACHE WITH SPLIT-INDEXES," the contents of which are hereby incorporated by reference in their entirety. Technical Field The present application relates generally to addressing a configurable Central Processing Unit (CPU) cache using a split index address structure. Background The performance of computer processors has increased exponentially over the past half of the century. Continued improvements in processing performance require continued development of new techniques and methods. One known performance improvement technique involves the use of a processor cache. Caches offer greatly improved data access times on main memory, but have limited storage capacity. Because of the performance enhancements they provide, it has been seen in the art that caches have been almost uniformly employed. Another technique for improving processor performance is to use multiple processors in parallel. In these scenarios, when the system uses multiple processors, the individual processing cores may share access to a single cache. This advantageously allows each processor to read data cached by the other processor. However, if each of the multiple processors accesses a different portion of the file in parallel, the memory accessed by each processor is likely to be spatially remote (i.e., likely to be located at rows and columns of memory that are remote from each other). For this reason, the likelihood that processors may request data mapped to the same cache line in such a scenario, thereby creating a conflict, is substantial. Cache conflicts are costly, causing the processor to instead read from main memory, resulting in considerable reduced performance. Thus, there is a need for improved cache performance for use by multiple processors in parallel when parallel processors are likely to access spatially distant portions of a file in memory. Disclosure of Invention In accordance with the disclosed subject matter, systems and methods for addressing a configurable cache with a split index are provided. In some embodiments, a method for storing elements from a main memory into a cache includes associating each of a plurality of cache lines from a cache memory with a different one of a plurality of indexes, wherein one of the plurality of indexes includes a first combined index, defining a first set of bits from a first address associated with a first memory location from the main memory as a first index portion and a second set of bits from the first address as a second index portion, generating the first combined index by concatenating the first index portion and the second index portion, and mapping at least the first memory location to a first cache line from the plurality of cache lines based on the first combined index. The method may also include defining a third set of bits from the first address as an offset, wherein the offset determines a location within the first cache line of the first memory location. The method may also include storing a plurality of blocks of data within the plurality of cache lines from frames of high definition video stored in the main memory. The method may also include scheduling read and write requests from the first processor and the second processor to the cache memory. The method may also include reading, via the first processor, a first data block located in a first column of the main memory, simultaneously reading, via the second processor, a second data block located in the first column of the main memory, and storing the first data block and the second data block in the cache memory. In some embodiments, a cache for storing data elements from a main memory includes a cache memory including a plurality of cache lines each referenced by a different index of a plurality of indexes, wherein one of the plurality of indexes includes a first combined index, an index configuration register configured to define a first set of bits from a first address associated with a first memory location from the main memory as a first index portion and a second set of bits from the first address as a second index portion, an index generation module configured to receive the first index portion and the second index portion as defined by the index configuration register and generate the first combined index by concatenating the first index portion and the second index portion, and a memory address mapping module to map at least the first memory location to a first cache line from the plurality of cache lines based on the first combined index. The index configuration register may be further configured to define a th