CN-114930459-B - Discharge current mitigation in memory arrays

Abstract

The application relates to discharge current mitigation in a memory array. The access line of the memory array may be divided into discrete segments, with each segment coupled with a driver for the access line through one or more vias corresponding to the segment. For example, a first segment of an access line may be coupled with a first set of memory cells, a second segment of the access line may be coupled with a second set of memory cells, and a driver may be coupled to the first segment through a first via and to the second segment through a second via. To access memory cells in the first set or the second set, the first segment of the access line and the second segment of the access line may be activated together by a common driver.

Inventors

• WANG HONGMEI
• SUN CHENCHENG
• A. Getty

Assignees

• 美光科技公司

Dates

Publication Date

20260505

Application Date

20201203

Priority Date

20191217

Claims (20)

1. 1. A memory apparatus, comprising: A first segment of an access line, the first segment coupled with a first set of memory cells; a second segment of the access line, the second segment being separate from the first segment and coupled with a second set of memory cells; A driver coupled with the first segment and the second segment; a first via coupled with the first segment, wherein the driver is coupled with the first segment through the first via, and A second via coupled with the second segment, wherein the driver is coupled with the first segment and the second segment through the first via, the second via, and at least one conductive line, and wherein each of the at least one conductive line is directly coupled with the driver.
2. 2. The memory device of claim 1, wherein the at least one conductive line comprises: A conductive line lower than the first segment and the second segment, wherein the first via and the second via are coupled with the conductive line, and wherein the driver comprises a transistor lower than the conductive line and coupled with the conductive line.
3. 3. The memory device of claim 1, wherein the at least one conductive line comprises: A first conductive line lower than the first segment and a second conductive line lower than the second segment, wherein the first via is coupled with the first conductive line and the second via is coupled with the second conductive line.
4. 4. The memory apparatus of claim 3, wherein the driver comprises a first transistor coupled with the first conductive line and a second transistor coupled with the second conductive line.
5. 5. The memory device of claim 4, wherein a gate of the first transistor is coupled with a gate of the second transistor.
6. 6. The memory device of claim 1, wherein: the first segment and the second segment each having a first resistivity, and The first via and the second via both have a second resistivity that is greater than the first resistivity.
7. 7. The memory device of claim 1, wherein: The first via being coupled to the first segment at a first location closer to an end of the first segment than a midpoint of the first segment, and The second via is coupled with the second segment at a second location closer to an end of the second segment than a midpoint of the second segment.
8. 8. The memory device of claim 1, wherein: the first segment and the second segment being at the same level of the memory device, and The first segment and the second segment are separated by a gap at the same level.
9. 9. The memory apparatus of claim 1, further comprising: A dielectric material between the first segment and the second segment at a first level including the first segment and the second segment, wherein the first segment is coupled with the second segment at a second level lower than the first level.
10. 10. The memory device of claim 1, wherein the second segment is collinear with the first segment.
11. 11. The memory apparatus of claim 1, wherein the first segment and the second segment are equal in length.
12. 12. The memory apparatus of claim 1, wherein the first segment and the second segment are not equal in length.
13. 13. The memory apparatus of claim 1, further comprising: one or more additional segments of the access line, each additional segment of the access line being collinear with the first segment and the second segment, and each additional segment of the access line being coupled with the driver and a corresponding set of additional memory cells.
14. 14. The memory apparatus of claim 1, wherein the driver is operable to activate the first segment and the second segment simultaneously to access memory cells in the first set of memory cells or the second set of memory cells.
15. 15. The memory device of claim 1, wherein: The access lines have addresses; Based at least in part on the address, the memory cells in the first set and the memory cells in the second set are both accessible, and The driver may be used to adjust a voltage of the first segment and a voltage of the second segment based at least in part on an access command associated with the address.
16. 16. The memory apparatus of claim 1, wherein the memory cells in the first and second sets each comprise a chalcogenide material.
17. 17. A method at a memory device, comprising: Receiving a command to perform an access operation for the memory cell; activating a first segment of an access line and a second segment of the access line in response to the command, the second segment being discontinuous with the first segment, wherein: The first segment is coupled with a first set of memory cells including the memory cell, and the second segment is coupled with a second set of memory cells not including the memory cell, The first segment is coupled to a driver through a first via and the second segment is coupled to the driver through a second via, The driver is coupled with the first segment and the second segment through the first via, the second via and at least one conductive line, an Each of the at least one conductive line is directly coupled with the driver, and The access operation is performed based at least in part on the activation in response to the command.
18. 18. The method as recited in claim 17, further comprising: an address of the access line is identified based at least in part on the command, wherein the activation in response to the command is based at least in part on the address of the access line.
19. 19. The method according to claim 17, wherein: the first segment is coupled to the driver by a conductive line, the first segment being parallel to the conductive line; The second segment being coupled to the driver by the conductive line, the second segment being parallel to the conductive line, and The activating in response to the command includes adjusting a voltage of the first segment and a voltage of the second segment simultaneously using the driver.
20. 20. The method according to claim 19, wherein: the driver includes a first transistor and a second transistor; the first segment is coupled with the first transistor through the first via and a first conductive line, the first segment being parallel to the first conductive line; The second segment is coupled to the second transistor through the second via and a second conductive line, the second segment being parallel to the second conductive line, and The activating in response to the command includes activating the first transistor and the second transistor simultaneously.

Description

Discharge current mitigation in memory arrays Cross reference This patent application is a national phase application of national patent application Ser. No. PCT/US 2020/0631100 entitled "discharge Current mitigation in memory array (DISCHARGE CURRENT MITIGATION IN A MEMORY ARRAY)" filed by Wang at month 12 and 3 of 2020, claiming U.S. patent application Ser. No. 17/085,154 entitled "discharge Current mitigation in memory array (DISCHARGE CURRENT MITIGATION IN A MEMORY ARRAY)" filed by Wang at month 10 and day 30 of 2020, and a priority of U.S. provisional patent application Ser. No. 16/717,944 entitled "discharge Current mitigation in memory array (DISCHARGE CURRENT MITIGATION IN A MEMORY ARRAY)" filed by Wang at month 12 and 17 of 2019, each of which is assigned to the present assignee and each of which is expressly incorporated herein by reference in its entirety. Technical Field The technical field relates to discharge current mitigation in memory arrays. Background Memory devices are widely used to store information in a variety of electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device to various states. For example, a binary memory cell may be programmed to one of two support states, often represented by a logic 1 or a logic 0. In some examples, a single memory cell may support more than two states, any of which may be stored. To access the stored information, the component may read or sense at least one stored state in the memory device. To store information, the component may write or program a state in the memory device. There are various types of memory devices and memory cells including magnetic hard disks, random Access Memories (RAMs), read Only Memories (ROMs), dynamic RAMs (DRAMs), synchronous Dynamic RAMs (SDRAM), ferroelectric RAMs (ferams), magnetic RAMs (MRAM), resistive RAMs (RRAM), flash memories, phase Change Memories (PCM), self-selected memories, chalcogenide memory technologies, and the like. The memory cells may be volatile or nonvolatile. Nonvolatile memory such as FeRAM can maintain its stored logic state for a long period of time even if no external power source is present. Volatile memory devices, such as DRAMs, may lose their stored state when disconnected from an external power source. Disclosure of Invention An apparatus is described. The apparatus may include a first segment of an access line coupled with a first set of memory cells, a second segment of the access line separate from the first segment and coupled with a second set of memory cells, and a driver coupled with the first segment and the second segment. A method is described. The method may include receiving a command to perform an access operation for a memory cell, activating a first segment of an access line and a second segment of the access line in response to the command, the second segment being discontinuous from the first segment, wherein the first segment is coupled with a first set of memory cells including the memory cell, and wherein the second segment is coupled with a second set of memory cells not including the memory cell, and performing the access operation based at least in part on the activating in response to the command. An apparatus is described. The apparatus may include a plurality of memory cells arranged in rows and columns, a plurality of word lines each coupled with a respective row of memory cells, and a plurality of bit lines each coupled with a respective column of memory cells, wherein each word line includes a plurality of discontinuous word line segments each coupled with a respective subset of the respective row of memory cells, and each bit line includes a plurality of discontinuous bit line segments each coupled with a respective subset of the respective column of memory cells. Drawings Fig. 1 illustrates an example of a memory die supporting discharge current mitigation in a memory array according to examples as disclosed herein. Fig. 2 illustrates an example of a memory array supporting discharge current mitigation in the memory array according to examples as disclosed herein. Fig. 3-5 illustrate examples of memory architectures supporting discharge current mitigation in a memory array according to examples as disclosed herein. Fig. 6 shows a block diagram of a memory array supporting discharge current mitigation in the memory array, in accordance with aspects of the present disclosure. FIG. 7 shows a flow chart illustrating one or more methods of supporting discharge current mitigation in a memory array in accordance with an example as disclosed herein. Detailed Description In some memory arrays, current discharge through the memory cells may result in current "spikes" (e.g., relatively high current discharge through the memory cells in a relatively short period of time), which may cause damage to the memory cells. Some such spikes may be caused