CN-114975282-B - Method for manufacturing semiconductor device

CN114975282BCN 114975282 BCN114975282 BCN 114975282BCN-114975282-B

Abstract

The invention discloses a manufacturing method of a semiconductor device, relates to the technical field of semiconductors, and is used for simultaneously improving carrier mobility of an NMOS transistor and a PMOS transistor of which device structures are all ring gate transistors. The manufacturing method comprises the steps of forming a first gate-all-around transistor on a first well region of a substrate and forming a second gate-all-around transistor on a second well region of the substrate. The first gate-all-around transistor has a first channel region with a crystal orientation perpendicular to a crystal orientation of a second channel region of the second gate-all-around transistor. Forming the first gate-all-around transistor on the first well region comprises forming a first stack structure on the first well region. The first stack structure includes a preformed layer, and first material layers and second material layers alternately formed on the preformed layer. The second material layer is located at the topmost layer in the first stacked structure. And carrying out transverse thinning treatment on each first material layer so that the width of the rest part of each first material layer is equal to the width of the first channel region.

Inventors

LI YONGLIANG
ZHANG JIAYI
JIA XIAOFENG
ZHAO FEI
YIN HUAXIANG
LUO JUN
WANG WENWU

Assignees

中国科学院微电子研究所

Dates

Publication Date: 20260505
Application Date: 20220412

Claims (10)

1. A method of manufacturing a semiconductor device, comprising: Providing a substrate, wherein the substrate is provided with a first well region and a second well region; forming a first gate-all-around transistor on the first well region and forming a second gate-all-around transistor on the second well region; the first gate-all-around transistor and the second gate-all-around transistor are opposite in conductivity type; the first gate-all-around transistor comprises a first channel and a first gate stack surrounding the periphery of a first channel region of the first channel, wherein the first gate stack surrounds the periphery of each layer of nanowire or sheet included in the first channel region; the second gate-all-around transistor comprises a second channel and a second gate stack surrounding the periphery of a second channel region of the second channel, wherein the second gate stack surrounds the periphery of each layer of nanowire or sheet contained in the second channel region, the crystal orientation of the first channel region is perpendicular to that of the second channel region, and the materials of the first channel and the second channel are different, the first gate-all-around transistor is formed on the first well region and comprises the steps of forming a first stacked structure on the first well region, forming a first material layer and a second material layer alternately formed on the first material layer and the second material layer along the thickness direction of the substrate, forming the second material layer on the first stacked structure, wherein the second material layer is positioned at the top layer in the first stacked structure, the length of the first stacked structure is equal to that of the first channel region, performing transverse thinning treatment on each layer of the first material layer contained in the first stacked structure, so that the width of each layer of the first stacked structure is equal to that the first well region is removed, and the remaining layers of the first stacked structure are at least partially removed from the first well region, and forming a part of the first channel in the first channel region by the residual part of the first material layer after the transverse thinning treatment; Forming a first gate-all-around transistor on the first well region and a second gate-all-around transistor on the second well region comprises forming a first fin structure and a second fin structure with the same structure on the substrate; the first fin structure is positioned on the first well region, the second fin structure is positioned on the second well region, the first fin structure and the second fin structure are provided with a source forming region, a drain forming region and a transition region positioned between the source forming region and the drain forming region, a sacrificial gate and a side wall which are formed to cover the transition region of the first fin structure and the periphery of the transition region of the second fin structure, the side wall is at least formed on two sides of the sacrificial gate along the width direction, the part of the first fin structure covered by the sacrificial gate is the first stacking structure, the part of the second fin structure covered by the sacrificial gate is the second stacking structure, the source forming region and the drain forming region of the first fin structure are processed to form a first source region and a first drain region which are included in the first ring gate transistor, the source forming region and the drain forming region of the second fin structure are processed to form a second ring gate region which is included in the second ring gate transistor, and the second drain region which is included in the second ring gate transistor is formed in the second fin structure; The forming of the second gate-all-around transistor on the second well region after the removing of the sacrificial gate or after the forming of the first gate-all-around transistor on the first well region further comprises selectively removing at least the first material layer on the second well region such that the second material layer on the second well region forms a portion of the second channel within the second channel region, and forming the second gate stack at least at the periphery of the second channel region.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the first gate-all-around transistor is a PMOS transistor, and a crystal orientation of the first channel region is a [110] crystal orientation; The second gate-all-around transistor is an NMOS transistor, and the crystal orientation of the second channel region is [100 ].
3. The method for manufacturing a semiconductor device according to claim 1, wherein the number of layers of the first material layer is equal to the number of layers of the second material layer, the first material layer located at a lowermost layer is in contact with the preformed layer, or, The number of the first material layers is one less than that of the second material layers, and the second material layers positioned at the bottommost layer are in contact with the preformed layer.
4. The method of manufacturing a semiconductor device according to claim 1, wherein a thickness of the first material layer is larger than a thickness of the second material layer, and/or, The thickness of the first material layer is 10 nm-60 nm, and/or, The thickness of the second material layer is 5 nm-20 nm.
5. The method according to claim 1, wherein the first material layer is Si 1-x Ge x , wherein x is 0≤1; The material of the second material layer is Si 1-y Ge y , wherein y is more than or equal to 0 and less than or equal to 1, and |x-y| is more than or equal to 0.2.
6. The method according to claim 1, wherein the preformed layer includes a first preformed portion and/or a second preformed portion, wherein the first preformed portion is made of Si, and the second preformed portion is made of Si 1-z Ge z , wherein 0<z is equal to or less than 1; In the case where the preformed layer includes the first preformed portion and the second preformed portion, the second preformed portion is located on the first preformed portion.
7. The method according to claim 1, wherein the lateral thinning process is performed on each of the first material layers included in the first stacked structure by using a quasi-atomic layer etching process.
8. The method according to claim 7, wherein the performing the lateral thinning process on each of the first material layers included in the first stacked structure using the quasi-atomic layer etching process includes: Under the mask action of a mask layer, carrying out selective oxidation treatment on each first material layer included in the first stacked structure, so that each first material layer included in the first stacked structure is transversely thinned by a fixed thickness, and an oxide layer is formed on the side wall of the rest part of each first material layer included in the first stacked structure; Removing the oxide layer; and repeating the operation until the width of the rest part of each first material layer included in the first stacking structure is equal to the width of the first channel region.
9. The method for manufacturing a semiconductor device according to claim 1, wherein the second material layer located at a lowermost layer is in contact with the preformed layer; the at least selectively removing the first material layer on the second well region is to selectively remove the preformed layer on the second well region and the first material layer on the second well region.
10. The method for manufacturing a semiconductor device according to claim 1, wherein the first material layer located at a lowermost layer is in contact with the preformed layer; The at least selectively removing the second material layer located on the first well region is to selectively remove the preformed layer located on the first well region and the second material layer located on the first well region.

Description

Method for manufacturing semiconductor device Technical Field The present invention relates to the field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor device. Background The gate-all-around transistor has the advantages of higher gate control capability and the like compared with the planar transistor and the fin field effect transistor, so that the working performance of the CMOS device can be improved when the NMOS transistor and the PMOS transistor included in the CMOS device are all gate-all-around transistors. However, when the device structures of the NMOS transistor and the PMOS transistor are all existing gate-all-around transistors, the operation performance of the CMOS device including the NMOS transistor and the PMOS transistor may be poor. Disclosure of Invention The invention aims to provide a manufacturing method of a semiconductor device, which is used for improving carrier mobility of an NMOS transistor and a PMOS transistor and further improving conductivity of the CMOS device under the condition that the device structures of the NMOS transistor and the PMOS transistor included in the CMOS device are all ring gate transistors. In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device, the method comprising: a substrate is provided. The substrate has a first well region and a second well region. A first gate-all-around transistor is formed on the first well region and a second gate-all-around transistor is formed on the second well region. The first and second gate-all-around transistors are opposite in conductivity type. The first gate-all-around transistor includes a first channel, and a first gate stack surrounding a periphery of a first channel region provided in the first channel. The second gate-all-around transistor includes a second channel, and a second gate stack surrounding a periphery of a second channel region provided in the second channel. The first channel region has a crystal orientation perpendicular to a crystal orientation of the second channel region. Wherein forming the first gate-all-around transistor on the first well region comprises: A first stack structure is formed on the first well region. The first stacked structure includes a preformed layer, and first material layers and second material layers alternately formed on the preformed layer along a thickness direction of the substrate. The second material layer is positioned at the topmost layer in the first stacked structure, and the length of the first stacked structure is equal to that of the first channel region. And carrying out transverse thinning treatment on each first material layer included in the first stacking structure so that the width of the rest part of each first material layer included in the first stacking structure is equal to the width of the first channel region. Compared with the prior art, in the manufacturing method of the semiconductor device, the conductivity types of the first gate-all-around transistor and the second gate-all-around transistor formed on the substrate are opposite, namely one of the first gate-all-around transistor and the second gate-all-around transistor can be an NMOS transistor, and the other one of the first gate-all-around transistor and the second gate-all-around transistor can be a PMOS transistor. That is, the device structures of the NMOS transistor and the PMOS transistor may be all gate-all-around transistors, so that the gate control capability of the NMOS transistor and the PMOS transistor may be simultaneously improved, and short channel effects may be suppressed. In addition, the first gate-all-around transistor has a first channel region with a crystal orientation perpendicular to a crystal orientation of a second channel region of the second gate-all-around transistor. Based on this, in practical applications, taking the first gate-all-around transistor as a PMOS transistor and the second gate-all-around transistor as an NMOS gate-all-around transistor as an example, if the first channel region of the first gate-all-around transistor is in the [110] crystal orientation and the second channel region of the second gate-all-around transistor is in the [100] crystal orientation, compared with the prior art in which both the NMOS transistor and the PMOS transistor use the gate-all-around transistor having the channel in the [100] crystal orientation, the method for manufacturing the semiconductor device provided by the present invention can simultaneously improve the carrier mobility of the NMOS transistor and the PMOS transistor and enhance the conductivity of the manufactured semiconductor device. In addition, the manufacturing method of the semiconductor device provided by the invention obtains the first channel region by transversely thinning each first material layer included in the first stacking structure, does not need additional procedures such