CN-114975584-B - Semiconductor device and method for manufacturing semiconductor device

Abstract

The present application relates to a semiconductor device and a method for manufacturing the semiconductor device. A semiconductor device includes a gate structure including a plurality of conductive layers and a plurality of insulating layers alternately stacked, a channel layer penetrating the gate structure, a plurality of memory patterns respectively located between the channel layer and the plurality of conductive layers, a plurality of air gaps located between the plurality of memory patterns, and a sealing layer including a plurality of first portions respectively including the air gaps and a second portion extending between the plurality of memory patterns.

Inventors

• JIANG RENQIU
• Jin Changhan

Assignees

• 爱思开海力士有限公司

Dates

Publication Date

20260512

Application Date

20210806

Priority Date

20210218

Claims (14)

1. 1. A semiconductor device, the semiconductor device comprising: A gate structure including a plurality of conductive layers and a plurality of insulating layers alternately stacked; a channel layer penetrating the gate structure; a plurality of memory patterns respectively located between the channel layer and the plurality of conductive layers; A plurality of air gaps between the plurality of memory patterns, and A sealing layer including a plurality of first portions respectively including the air gaps and a second portion extending between the plurality of memory patterns and the channel layer, Wherein the sealing layer does not vertically overlap the conductive layer.
2. 2. The semiconductor device of claim 1, wherein the sealing layer is a single layer comprising the first portion and the second portion.
3. 3. The semiconductor device according to claim 1, further comprising a plurality of barrier patterns respectively located between the memory pattern and the conductive layer.
4. 4. The semiconductor device of claim 3, wherein each of the first portions includes a first region between the plurality of barrier patterns and a second region between the plurality of memory patterns.
5. 5. The semiconductor device according to claim 4, wherein a width of the first region is narrower than a width of the second region.
6. 6. The semiconductor device according to claim 4, wherein the second region has a circular cross section.
7. 7. The semiconductor device according to claim 1, wherein each of the plurality of memory patterns includes a first surface and a second surface having a concave shape, and The first surface and the second surface are in contact with the sealing layer.
8. 8. A method of manufacturing a semiconductor device, the method comprising the steps of: forming a laminated structure including a plurality of first material layers and a plurality of second material layers which are alternately laminated; forming a first opening through the laminated structure; Forming a plurality of sacrificial patterns on the second material layer; forming a barrier layer surrounding the sacrificial pattern in the first opening; Forming a memory pattern between the plurality of sacrificial patterns; exposing the sacrificial pattern by etching a portion of the barrier layer exposed by the memory pattern; forming an air gap by removing the sacrificial pattern, and A sealing layer is formed in the air gap, Wherein the sealing layer does not vertically overlap the first material layer.
9. 9. The method of claim 8, wherein forming the sacrificial pattern comprises: Forming a plurality of first material patterns on the first material layer, and The sacrificial pattern is formed between the plurality of first material patterns.
10. 10. The method of claim 8, wherein forming the sealing layer comprises: Forming the sealing layer including a first portion formed in the air gap and a second portion formed in the first opening, and Etching the second portion of the sealing layer.
11. 11. The method of claim 10, further comprising the step of: forming a tunnel insulating layer in the first opening, and And forming a channel layer in the tunnel insulating layer.
12. 12. The method of claim 8, wherein in the step of forming the barrier layer, the barrier layer is formed by oxidizing the sacrificial pattern and the first material layer.
13. 13. The method of claim 8, wherein in the step of forming the sealing layer, the sealing layer including a first portion formed in the air gap and a second portion formed in the first opening is formed, and the second portion serves as a tunnel insulating layer.
14. 14. The method of claim 8, wherein each of the memory patterns includes a first surface and a second surface having a concave shape, and in forming the memory patterns The first surface and the second surface are in contact with the sealing layer when the sealing layer is formed.

Description

Semiconductor device and method for manufacturing semiconductor device Technical Field The present disclosure relates generally to electronic devices, and more particularly, to a semiconductor device and a method of manufacturing the semiconductor device. Background The degree of integration of a semiconductor device is mainly determined by the area occupied by the unit memory cells. As the improvement of the integration level of a semiconductor device in which memory cells are formed over a substrate in a single layer form reaches a limit, a three-dimensional semiconductor device in which memory cells are stacked over a substrate has recently been proposed. Various structures and fabrication methods have been developed to improve the operational reliability of three-dimensional semiconductor devices. Disclosure of Invention According to an aspect of the present disclosure, there may be provided a semiconductor device including a gate structure including a plurality of conductive layers and a plurality of insulating layers alternately stacked, a channel layer penetrating the gate structure, a plurality of memory patterns respectively located between the channel layer and the plurality of conductive layers, a plurality of air gaps located between the plurality of memory patterns, and a sealing layer including a plurality of first portions respectively including the air gaps and a second portion extending between the plurality of memory patterns. According to another aspect of the present disclosure, there may be provided a method of manufacturing a semiconductor device, the method including forming a stacked structure including a plurality of first material layers and a plurality of second material layers alternately stacked, forming a first opening penetrating the stacked structure, forming a plurality of sacrificial patterns on the second material layers, forming a barrier layer surrounding the sacrificial patterns in the first opening, forming a memory pattern between the plurality of sacrificial patterns, exposing the sacrificial patterns by etching portions of the barrier layer exposed by the memory pattern, forming an air gap by removing the sacrificial patterns, and forming a sealing layer in the air gap. Drawings Examples of embodiments will now be described more fully hereinafter with reference to the accompanying drawings, which, however, may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. In the drawings, the size may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements or one or more intervening elements may also be present. Like numbers refer to like elements throughout. Fig. 1A, 1B, and 1C are diagrams illustrating a structure of a semiconductor device according to an embodiment of the present disclosure. Fig. 2A, 2B, 2C, 2D, 2E, 2F, 2G, and 2H are diagrams illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 3A, 3B, 3C, 3D, and 3E are diagrams illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 4A, 4B, and 4C are diagrams illustrating a structure of a semiconductor device according to an embodiment of the present disclosure. Fig. 5A, 5B, 5C, 5D, 5E, 5F, and 5G are diagrams illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 6A and 6B are diagrams illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 7A and 7B are diagrams illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 8A, 8B, and 8C are diagrams illustrating a structure of a semiconductor device according to an embodiment of the present disclosure. Fig. 9A, 9B, 9C, 9D, 9E, 9F, 9G, 9H, 9I, 9J, and 9K are diagrams illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 10A, 10B, and 10C are diagrams illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 11A, 11B, 11C, 11D, and 11E are diagrams illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 12 is a diagram illustrating a memory system according to an embodiment of the present disclosure. Fig. 13 is a diagram illustrating a memory system according to an embodiment of the present disclosure. Fig. 14 is a diagram illustrating a memory system according to an embodiment of the present disclosure. Fig. 15 is a diagram illustrating a memory system according to an embodiment of the present disclosure. Fig. 16 is a diagram illustrating a memory system according to an embodimen