CN-114977796-B - Chip output current control method and control circuit

CN114977796BCN 114977796 BCN114977796 BCN 114977796BCN-114977796-B

Abstract

The invention discloses a chip output current control method and a control circuit, wherein the chip output current control method comprises the steps of generating output bias current according to an accessed reference voltage and outputting the output bias current to an output end of a chip; and adjusting the current of the output end according to the input bias current so that the current of the output end is the difference current of the output bias current and the input bias current. The invention generates output bias current according to the accessed reference voltage and outputs the output bias current to the output end of the chip, and generates input bias current according to the accessed reference voltage to regulate the current of the output end so that the current of the output end is the difference current between the output bias current and the input bias current, and the chip can regulate the output current of the chip by adopting a differential current output mode to ensure the precision requirement of the output current of the chip, so that tiny current can be output.

Inventors

YAO RUIKUN
JI JINGWEN

Assignees

深圳君略科技有限公司

Dates

Publication Date: 20260512
Application Date: 20220630

Claims (8)

1. A chip output current control method, comprising: generating an output bias current according to the accessed reference voltage and outputting the output bias current to an output end of the chip, wherein the output bias current comprises a first adjustable current generated according to the reference voltage; generating an input bias current according to an accessed reference voltage, including generating a second adjustable current according to the reference voltage; And regulating the current of the output end according to the input bias current so that the current of the output end is the difference current between the output bias current and the input bias current, wherein the output bias current and the input bias current are biased by adopting microampere-level current.
2. A chip output current control circuit, comprising: the bias current output module is connected with the reference voltage Vref and the output end OUT of the chip output current control circuit, and is used for generating output bias current according to the reference voltage and outputting the output bias current to the output end of the chip; the bias current input module is connected with the reference voltage Vref and the output end OUT and is used for generating input bias current according to the reference voltage so as to regulate the current of the output end; The current of the output end is the difference current of the output bias current and the input bias current, and the output bias current and the input bias current are biased by adopting microampere-level current.
3. The chip output current control circuit according to claim 2, wherein the bias current output module comprises a first adjustable current output unit and a first MOS tube; The first adjustable current output unit is connected with the reference voltage and generates a first adjustable current according to the reference voltage; The grid electrode of the first MOS tube is connected with the first adjustable current output unit, the drain electrode of the first MOS tube is connected with the output end, the source electrode of the first MOS tube is connected with a power supply, and the first MOS tube is used for outputting the output bias current to the output end according to the first adjustable current.
4. The chip output current control circuit of claim 3, wherein the first adjustable current output unit comprises a first operational amplifier, a second MOS transistor and a first resistor, wherein, The inverting input end of the first operational amplifier is connected with the reference voltage, the non-inverting input end of the first operational amplifier is connected with one end of the first resistor, and the output end of the first operational amplifier is connected with the grid electrode of the second MOS tube; The grid electrode of the second MOS tube is also connected with the grid electrode of the first MOS tube, the drain electrode of the second MOS tube is connected with one end of the first resistor, and the source electrode of the second MOS tube is connected with a power supply; the other end of the first resistor is grounded, wherein the first MOS tube and the second MOS tube form a current mirror structure, and the first MOS tube copies the current of the second MOS tube in proportion.
5. The chip output current control circuit of claim 2, wherein the bias current input module comprises a second adjustable current output unit, a third MOS transistor and an input bias current unit, wherein, The second adjustable current output unit is connected with the reference voltage and generates a second adjustable current according to the reference voltage; the grid electrode of the third MOS tube is connected with the second adjustable current output unit, the drain electrode of the third MOS tube is connected with the input bias current unit, the source electrode of the third MOS tube is connected with a power supply, and the third MOS tube is used for generating an output current to the input bias current unit according to the second adjustable current; the input bias current unit is connected with the drain electrode of the third MOS tube and is used for converting the output current into the input bias current.
6. The chip output current control circuit of claim 5, wherein the second adjustable current output unit comprises a second operational amplifier, a fourth MOS transistor and a second resistor, wherein, The inverting input end of the second operational amplifier is connected with the reference voltage, the non-inverting input end of the second operational amplifier is connected with one end of the second resistor, and the output end of the second operational amplifier is connected with the grid electrode of the fourth MOS tube; The grid electrode of the fourth MOS tube is also connected with the grid electrode of the third MOS tube, the drain electrode of the fourth MOS tube is connected with one end of the second resistor, and the source electrode of the fourth MOS tube is connected with a power supply; The other end of the second resistor is grounded.
7. The chip output current control circuit of claim 6, wherein the input bias current unit comprises a fifth MOS transistor and a sixth MOS transistor, wherein, The grid electrode of the fifth MOS tube is connected with the grid electrode of the sixth MOS tube, the drain electrode of the fifth MOS tube is connected with the drain electrode of the third MOS tube, and the source electrode of the fifth MOS tube is grounded; the drain electrode of the sixth MOS tube is connected with the output end, and the source electrode of the sixth MOS tube is grounded.
8. The chip output current control circuit of claim 7, wherein the third MOS transistor and the fourth MOS transistor form a current mirror structure, the third MOS transistor replicates the current of the fourth MOS transistor in proportion, the fifth MOS transistor and the sixth MOS transistor form a current mirror structure, and the sixth MOS transistor replicates the current of the fifth MOS transistor in proportion.

Description

Chip output current control method and control circuit Technical Field The invention relates to the technical field of integrated circuits, in particular to a chip output current control method and a control circuit. Background The working bias current of the internal MOS circuit of the integrated circuit chip needs to meet a certain size, and too small bias current can cause poor consistency or noise interference and influence the stability of the current. In order to make the chip output a minute current (100 nA level), the internal circuit of the chip also operates in a minute current bias state (100 nA level), and the MOS transistor operates in a subthreshold region. Operating current formula of MOS tubeWhen V GS-Vt approaches 0, the current is infinitesimal, and a small current bias can be obtained. In practice, the threshold voltage Vt of the MOS transistor will vary because of manufacturing process variations, V t＝V0+dVt,V0 is the ideal threshold voltage of the device, and dV t is the mismatched threshold voltage caused by the process variations. When it is desired to obtain a current value of 0 (or close to 0), V GS-Vt＝VGS-V0 = 0 is ideal, i.e In practice the V GS-Vt＝VGS-(V0+dVt)＝-dVt of the present invention,The effect of dV t is serious, namely the bias current deviation of the MOS transistor is great due to the process mismatch of the device. When the MOS tube is provided with the bias current of 100nA, the actual output current can be 0 or 200nA, and the requirements of + -5% deviation cannot be met, so that the output current of the produced chip cannot be accurately controlled. Accordingly, the prior art is still in need of improvement and development. Disclosure of Invention In view of the above-mentioned shortcomings of the prior art, the present invention is directed to a method and a circuit for controlling chip output current, so as to solve the problem that the chip output current cannot be accurately controlled due to the manufacturing process deviation of the MOS transistor in the existing chip output current control circuit. The technical scheme of the invention is as follows: a chip output current control method, comprising: Generating output bias current according to the accessed reference voltage and outputting the bias current to the output end of the chip; generating an input bias current according to the accessed reference voltage; and regulating the current of the output end according to the input bias current so that the current of the output end is the difference current of the output bias current and the input bias current. According to a further arrangement of the present invention, the step of generating the output bias current according to the accessed reference voltage and outputting the bias current to the output terminal of the chip includes: Generating a first adjustable current according to the reference voltage; and outputting the output bias current to the output end according to the first adjustable current. According to a further arrangement of the invention, the step of generating the input bias current from the accessed reference voltage comprises: generating a second adjustable current according to the reference voltage; generating an output current according to the second adjustable current; the input bias current is generated from the output current. Based on the same inventive concept, the invention also provides a chip output current control circuit, which comprises: The bias current output module is connected with a reference voltage and is used for generating output bias current according to the reference voltage and outputting the output bias current to the output end of the chip; the bias current input module is connected with the reference voltage and is used for generating input bias current according to the reference voltage so as to regulate the current of the output end; the current of the output end is the difference current of the output bias current and the input bias current. The bias current output module comprises a first adjustable current output unit and a first MOS tube; The first adjustable current output unit is connected with the reference voltage and generates a first adjustable current according to the reference voltage; The grid electrode of the first MOS tube is connected with the first adjustable current output unit, the drain electrode of the first MOS tube is connected with the output end, the source electrode of the first MOS tube is connected with a power supply, and the first MOS tube is used for outputting the output bias current to the output end according to the first adjustable current. The invention further provides that the first adjustable current output unit comprises a first operational amplifier, a second MOS tube and a first resistor, wherein, The inverting input end of the first operational amplifier is connected with the reference voltage, the non-inverting input end of the first operational amplifier is connecte