CN-115020473-B - Semiconductor structure and preparation method thereof

Abstract

The embodiment of the disclosure provides a semiconductor structure and a preparation method thereof, wherein the semiconductor structure comprises a substrate, a grid dielectric layer, a plurality of word lines extending along a first direction, a plurality of semiconductor columns arranged along the first direction, a plurality of gate dielectric layers, a plurality of semiconductor layers, a plurality of air gaps, and a plurality of air gaps, wherein the substrate is provided with a plurality of semiconductor columns which are arranged at intervals, each semiconductor column comprises a first source drain region, a first channel region, a second channel region and a second source drain region which are sequentially distributed along a direction far away from the surface of the substrate, the grid dielectric layers surround the side surfaces of the semiconductor columns of the first channel region, each word line surrounds the plurality of semiconductor columns which are arranged along the first direction, the word line surrounds the first channel region and the second channel region in the semiconductor columns, the grid dielectric layers are arranged between the word line and the semiconductor columns of the first channel region, and the air gaps are arranged between the word line and the semiconductor columns of the second channel region. Embodiments of the present disclosure are at least advantageous for reducing gate-induced drain leakage current of semiconductor structures.

Inventors

• LIU YOUMING

Assignees

• 长鑫存储技术有限公司

Dates

Publication Date

20260512

Application Date

20220530

Claims (15)

1. 1. A semiconductor structure, comprising: The semiconductor device comprises a substrate, wherein the substrate is provided with a plurality of semiconductor columns which are arranged at intervals, and each semiconductor column comprises a first source drain region, a first channel region, a second channel region and a second source drain region which are sequentially distributed along the direction away from the surface of the substrate; The gate dielectric layer surrounds the side face of the semiconductor column of the first channel region; A plurality of word lines extending along a first direction, each word line surrounding a plurality of the semiconductor pillars arranged along the first direction, the word lines surrounding the first channel region and the second channel region in the semiconductor pillars, the word lines and the semiconductor pillars of the first channel region having the gate dielectric layer therebetween, the word lines and the semiconductor pillars of the second channel region having an air gap therebetween; The word line comprises a first conductive layer surrounding the semiconductor pillar of the first channel region; a second conductive layer, the second conductive layer being located on the surface of the first conductive layer and surrounding the semiconductor pillars of the second channel region, and the second conductive layer being of a material different from the material of the first conductive layer; The bottom surface of the first conductive layer is flush with the bottom surface of the gate dielectric layer, the first conductive layer exposes a part of the side surface of the gate dielectric layer, and the second conductive layer is also positioned on the side surface of the gate dielectric layer which is exposed by the first conductive layer and is partially high.
2. 2. The semiconductor structure of claim 1, wherein a ratio of a length of said gate dielectric layer to a length of said air gap in a direction away from said substrate surface is greater than 1:3.
3. 3. The semiconductor structure of claim 1, wherein a thickness of said gate dielectric layer is greater than or equal to a width of said air gap in said first direction.
4. 4. The semiconductor structure of claim 3, wherein a width of said air gap in said first direction is in a range of 1-5 nm.
5. 5. The semiconductor structure of claim 1, wherein a work function value of a material of the first conductive layer is different from a work function value of a material of the second conductive layer.
6. 6. The semiconductor structure of claim 1, further comprising a wordline cover covering the wordline top surface and covering the top opening of the air gap.
7. 7. The semiconductor structure of claim 1, further comprising: A plurality of bit lines extending along a second direction, each bit line being located between the plurality of semiconductor pillars arranged along the second direction and the substrate, and the bit lines being electrically connected to the first source drain regions; and the isolation layers are positioned between the bit lines and the word lines and are also positioned between adjacent word lines and between adjacent bit lines.
8. 8. The semiconductor structure of claim 7, wherein the isolation layer comprises: The first isolation layers are positioned between the adjacent semiconductor columns and between the adjacent bit lines, and the top surfaces of the first isolation layers are in contact with the bottom surfaces of the word lines and the bottom surfaces of the gate dielectric layers; the second isolation layer extends along the first direction and penetrates through the first isolation layer between the adjacent semiconductor columns arranged along the second direction, the second isolation layer is located between the adjacent word lines, and the top surface of the second isolation layer is higher than the top surface of the word line.
9. 9. A method of fabricating a semiconductor structure, comprising: Providing a substrate, wherein the substrate is provided with a plurality of semiconductor columns which are arranged at intervals, and the semiconductor columns comprise a first source drain region, a first channel region, a second channel region and a second source drain region which are sequentially distributed along the direction away from the surface of the substrate; forming a gate dielectric layer, wherein the gate dielectric layer surrounds the side surface of the semiconductor column of the first channel region; Forming a plurality of word lines extending along a first direction, wherein each word line surrounds a plurality of semiconductor columns arranged along the first direction, the word lines surround the first channel region and the second channel region in the semiconductor columns, the gate dielectric layer is arranged between the word lines and the semiconductor columns of the first channel region, and an air gap is arranged between the word lines and the semiconductor columns of the second channel region; The process for forming the gate dielectric layer comprises the following steps: forming a sacrificial layer on the side surface of the semiconductor column of the second channel region; Oxidizing the side surface of the semiconductor column of the first channel region to form the gate dielectric layer; and removing the sacrificial layer.
10. 10. The method of claim 9, further comprising forming a first spacer layer and a second spacer layer on the substrate, the first spacer layer being located between adjacent ones of the semiconductor pillars, the first spacer layer having a top surface that is lower than a top surface of the semiconductor pillars, the second spacer layer extending in the first direction through the first spacer layer between adjacent ones of the semiconductor pillars, and the second spacer layer having a top surface that is higher than a top surface of the semiconductor pillars of the second channel region; In the step of forming the sacrificial layer, the sacrificial layer is further formed on the side face of the second isolation layer, and the etching rate of the sacrificial layer is different from that of the second isolation layer by the same etching process.
11. 11. The method of fabricating a semiconductor structure of claim 10, wherein the process step of forming the sacrificial layer comprises: forming a protective layer which is positioned on the top surface of the first isolation layer and covers the side surface of the semiconductor column of the first channel region; forming a sacrificial film, wherein the sacrificial film is positioned on the top surface of the protective layer, the side surface of the semiconductor column of the second channel region and the side surface of the second isolation layer; and removing the sacrificial film on the top surface of the protective layer, and taking the remaining sacrificial film as the sacrificial layer.
12. 12. The method of claim 11, wherein the sacrificial film is silicon nitride, the second isolation layer is silicon nitride, and after removing the sacrificial film on the top surface of the protective layer, plasma treating the remaining sacrificial film to make the etching rate of the sacrificial layer different from the etching rate of the second isolation layer by the same etching process.
13. 13. The method of manufacturing a semiconductor structure of claim 9, further comprising, prior to forming the word line: forming an epitaxial layer on the side surface of the semiconductor column in the second channel region by adopting an epitaxial process; In the process step of forming the word line, the word line covers the side surface of the epitaxial layer; after forming the word lines, the epitaxial layer is removed to form the air gaps.
14. 14. The method of manufacturing a semiconductor structure of claim 13, wherein the process step of forming the word line comprises: Forming a first conductive layer which covers the side surface of the gate dielectric layer and surrounds the semiconductor column of the first channel region; And forming a second conductive layer on the top surface of the first conductive layer, wherein the second conductive layer covers the side surface of the epitaxial layer and surrounds the semiconductor column of the second channel region.
15. 15. The method of manufacturing a semiconductor structure of claim 14, wherein the process step of forming the first conductive layer comprises: forming a first conductive film surrounding the semiconductor pillars of the first and second channel regions; and etching back to remove part of the first conductive film until the top surface of the remaining first conductive film is lower than the top surface of the gate dielectric layer, wherein the remaining first conductive film is used as the first conductive layer.

Description

Semiconductor structure and preparation method thereof Technical Field The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof. Background As the integration density of dynamic memories has advanced toward higher levels, there has been a growing demand for the arrangement of transistors in dynamic memory array structures and for the size of the transistors. When the fully-surrounding gate transistor structure is used as a transistor in the dynamic memory, smaller pattern size can be obtained under given process conditions, which is beneficial to increasing the integration density of the dynamic memory. While research is being conducted on the manner in which dynamic memory structures are arranged and how the dimensions of dynamic memory structures are scaled down, there is also a need to improve the electrical performance of small-sized dynamic memories. In particular, as the size of the dynamic memory structure is reduced, in the dynamic memory structure, the influence of GIDL (gate-induced DRAIN LEAKAGE gate induced drain leakage current) on the electrical performance of the semiconductor structure increases due to the reduction of the separation distance between the gate electrode layer and the semiconductor channel. Disclosure of Invention The embodiment of the disclosure provides a semiconductor structure and a preparation method thereof, which are at least beneficial to reducing the gate-induced drain leakage current of the semiconductor structure. An aspect of the disclosed embodiment provides a semiconductor structure, which comprises a substrate, a gate dielectric layer, a plurality of word lines extending along a first direction, a plurality of semiconductor columns arranged along the first direction, a gate dielectric layer between the word lines and the semiconductor columns of the first channel region, and an air gap between the word lines and the semiconductor columns of the second channel region, wherein the substrate is provided with a plurality of semiconductor columns arranged at intervals, the semiconductor columns comprise a first source drain region, a first channel region, a second channel region and a second source drain region, the first channel region, the second channel region and the second source drain region are sequentially distributed along a direction far away from the surface of the substrate, the gate dielectric layer surrounds the side surface of the semiconductor columns of the first channel region, the word lines extend along the first direction, each word line surrounds the plurality of semiconductor columns arranged along the first direction, the word lines surround the first channel region and the second channel region in the semiconductor columns, and the gate dielectric layer is arranged between the word lines and the semiconductor columns of the first channel region. In some embodiments, the ratio of the length of the gate dielectric layer to the length of the air gap is greater than 1:3 in a direction away from the substrate surface. In some embodiments, the thickness of the gate dielectric layer is greater than or equal to the width of the air gap in the first direction. In some embodiments, the width of the air gap is in the range of 1-5 nm in the first direction. In some embodiments, the word line includes a first conductive layer surrounding the semiconductor pillars of the first channel region, and a second conductive layer on a surface of the first conductive layer surrounding the semiconductor pillars of the second channel region, the second conductive layer being of a different material than the first conductive layer. In some embodiments, the work function value of the material of the first conductive layer is different from the work function value of the material of the second conductive layer. In some embodiments, the bottom surface of the first conductive layer is flush with the bottom surface of the gate dielectric layer, and the first conductive layer exposes a portion of the side surface of the gate dielectric layer, and the second conductive layer is also located on a portion of the side surface of the gate dielectric layer exposed by the first conductive layer. In some embodiments, a word line cover layer is also included that covers the word line top surface and covers the top opening of the air gap. In some embodiments, the semiconductor device further comprises a plurality of bit lines extending along the second direction, each bit line being located between a plurality of semiconductor pillars arranged along the second direction and the substrate, and the bit lines being electrically connected to the first source drain regions, and an isolation layer located between the bit lines and the word lines, and further located between adjacent word lines and between adjacent bit lines. In some embodiments, the isolation layer comprises a first isolat