CN-115036288-B - Compensation capacitor layout in semiconductor device

Abstract

The application relates to a compensation capacitor layout in a semiconductor device. Apparatus and methods for arranging compensation capacitors are described. An example apparatus includes a first conductive layer including a portion, a second conductive layer, a contact coupled to the portion of the first conductive layer, a third conductive layer located between the first conductive layer and the second conductive layer, the third conductive layer coupled to the contact, one or more capacitor elements, wherein each capacitor element of the one or more capacitor elements includes one end coupled to the second conductive layer and another end coupled to the third conductive layer.

Inventors

• Baoban tree
• SUGIMOTO SATOSHI

Assignees

• 美光科技公司

Dates

Publication Date

20260505

Application Date

20211118

Priority Date

20210303

Claims (15)

1. 1. A semiconductor device, comprising: a first conductive layer including a power portion and an intermediate portion, the power portion configured to provide a supply voltage; A second conductive layer; A third conductive layer located between the first conductive layer and the second conductive layer; a contact between the first conductive layer and the third conductive layer, the contact including one end coupled to the middle portion of the first conductive layer and another end coupled to the third conductive layer, and One or more capacitor elements, wherein each of the one or more capacitor elements includes one end coupled to the second conductive layer and another end coupled to the third conductive layer, Wherein the power portion is included in a first power supply node, wherein the power supply voltage is a first power supply voltage, an Wherein the intermediate portion is included in an intermediate node that provides an intermediate voltage to the intermediate portion that is an average of the first supply voltage of the first supply node and a second supply voltage of a second supply node that is different from the first supply node.
2. 2. The apparatus of claim 1, wherein the third conductive layer comprises polysilicon.
3. 3. The apparatus of claim 1, wherein at least one capacitor element of the one or more capacitor elements comprises: a first electrode layer including a top portion coupled to the third conductive layer; A second electrode layer including a bottom portion coupled to the second conductive layer, and An insulating layer located between the first electrode layer and the second electrode layer and configured to insulate the first electrode layer from the second electrode layer.
4. 4. The apparatus of claim 3, wherein the first electrode layer comprises a cylindrical shape having a hollow body and further comprises the top portion and side portions, Wherein the insulating layer comprises a top portion and a side portion on the top portion and the side portion, respectively, of the first electrode layer.
5. 5. The apparatus of claim 4, wherein the second electrode layer comprises a pillar shape including a top surface and a side surface on the top portion and the side portion of the insulating layer, respectively, and further comprising a bottom surface on the second conductive layer.
6. 6. A semiconductor device, comprising: A first conductive layer including a first power portion, a second power portion, and first and second intermediate portions; an intermediate line in the first conductive layer, wherein the intermediate line is configured to couple the first intermediate portion to the second intermediate portion; A second conductive layer comprising a first portion and a second portion; A third conductive layer located between the first conductive layer and the second conductive layer, and including first and second portions coupled to the first and second intermediate portions of the first conductive layer, respectively; A first capacitor, comprising: one or more first capacitor elements including one end and another end, the one end coupled to the first portion of the third conductive layer and the other end coupled to the first portion of the second conductive layer; a first power contact including one end coupled to the first portion of the second conductive layer and another end coupled to the first power portion of the first conductive layer, and A first contact including one end coupled to the first portion of the third conductive layer and another end coupled to the first intermediate portion of the first conductive layer, and A second capacitor, comprising: One or more second capacitor elements including one end and another end, the one end coupled to the second portion of the third conductive layer and the other end coupled to the second portion of the second conductive layer; a second power contact including one end coupled to the second portion of the second conductive layer and another end coupled to the second power portion of the first conductive layer, and A second contact including one end coupled to the second portion of the third conductive layer and another end coupled to the second intermediate portion of the first conductive layer, Wherein the first power portion is configured to provide a first power supply voltage and the second power portion is configured to provide a second power supply voltage different from the first power supply voltage, Wherein the intermediate line is included in an intermediate node that provides an intermediate voltage to the intermediate line, and the intermediate voltage is an average of the first supply voltage and the second supply voltage.
7. 7. The apparatus of claim 6, wherein the first capacitor and the second capacitor comprise constant capacitance.
8. 8. The apparatus of claim 6, wherein the first capacitor and the second capacitor are disposed separately from each other.
9. 9. The apparatus of claim 6, wherein the first portion of the second conductive layer comprises one side and another side, and Wherein each of the one or more first capacitor elements further comprises a plurality of first power contacts including the first power contact coupled to the first portion of the second conductive layer at the one side and another first power contact coupled to the first portion of the second conductive layer at the other side.
10. 10. The apparatus of claim 6, wherein the third conductive layer further comprises a third portion, and Wherein the apparatus further comprises a pair of capacitors, the pair of capacitors comprising: A third capacitor, comprising: one or more third capacitor elements including one end coupled to the third portion of the third conductive layer and another end coupled to the first power portion, and A fourth capacitor, comprising: one or more fourth capacitor elements including one end coupled to the third portion of the third conductive layer and another end coupled to the second power portion.
11. 11. A semiconductor device, comprising: a first capacitor coupled to the first power line; a second capacitor coupled to the second power line; an intermediate line configured to couple the first capacitor to the second capacitor, wherein the first and second power lines and the intermediate line are contained in a first layer; wherein the intermediate line is included in an intermediate node that provides an intermediate voltage to the intermediate line, and the intermediate voltage is an average of voltages of the first power line and the second power line.
12. 12. The apparatus of claim 11, wherein the apparatus further comprises: a first contact configured to couple a node of the first capacitor in a second layer to the first power line in the first layer, an A second contact configured to couple another node of the first capacitor in an intermediate layer between the first layer and the second layer to the intermediate line in the first layer.
13. 13. The apparatus of claim 12, wherein the first capacitor is disposed in a first region and the second capacitor is disposed in a second region remote from the first region.
14. 14. The apparatus of claim 13, further comprising: a third capacitor and a fourth capacitor, which are disposed in the third region, Wherein the third capacitor and the fourth capacitor are coupled to the intermediate layer, the intermediate layer is included in the intermediate node, and Wherein the first region is smaller than the third region.
15. 15. The apparatus of claim 11, wherein at least one of the first capacitor or the second capacitor is a compensation capacitor configured to stabilize a supply voltage from at least one of the first power line or the second power line.

Description

Compensation capacitor layout in semiconductor device Technical Field The present application relates to semiconductor devices, and in particular to compensating capacitor layouts in semiconductor devices. Background High data reliability, high memory access speed, reduced chip size, and reduced power consumption are features required for semiconductor memories. Due to the reduced supply voltage and reduced chip size, the noise of the power supply can adversely affect performance. Compensation capacitors included in the devices have been used to stabilize power supplies. Semiconductor memory devices such as DRAMs (dynamic random access memories) include, for example, memory cell arrays having memory cells. The semiconductor memory device may include a compensation capacitor in a peripheral circuit region outside a memory cell array having a similar structure to the memory cells. The compensation capacitor included in the peripheral circuit region may include a capacitance unit of two or more capacitors connected in series. Since the voltage of each capacitor having a structure similar to the memory cell is smaller than the voltage difference between the power supply voltages (e.g., VDD and VSS), the voltage of the capacitive cell through two or more capacitors can be matched to the voltage difference between the power supply voltages. The capacitance unit of the two or more compensation capacitors connected in series may be included in an unused space in the logic circuit block in the peripheral circuit region. However, space in the logic circuit block in the peripheral circuit region that is smaller than the region for the two or more capacitors of the capacitive unit may remain unused. In order to efficiently use the space in the logic circuit block in the peripheral circuit region, a more flexible structure for the compensation capacitor included in the peripheral circuit region may be required. Disclosure of Invention In one aspect, the present disclosure provides an apparatus comprising a first conductive layer comprising a portion, a second conductive layer, a contact coupled to a portion of the first conductive layer, a third conductive layer located between the first conductive layer and the second conductive layer, and the third conductive layer coupled to the contact, and one or more capacitor elements, wherein each of the one or more capacitor elements comprises one end coupled to the second conductive layer and another end coupled to the third conductive layer. In another aspect, the present application provides an apparatus comprising a first conductive layer comprising a first power portion, a second power portion, and first and second intermediate portions, a second conductive layer comprising a first portion and a second portion, a third conductive layer between the first conductive layer and the second conductive layer, the third conductive layer comprising a first portion and a second portion coupled to the first intermediate portion of the first conductive layer and the second intermediate portion, respectively, a first capacitor comprising one or more first capacitor elements comprising one end and the other end, the one end being coupled to the first portion of the third conductive layer and the other end being coupled to the first portion of the second conductive layer, a first power contact comprising one end of the first portion of the second conductive layer and the other end of the first power portion being coupled to the first conductive layer, and a first contact comprising one end of the first portion of the third conductive layer and the other end of the first intermediate portion being coupled to the first conductive layer, and a second capacitor comprising one end and the other end of the second conductive layer, the second contact comprising the first portion of the second conductive layer and the other end being coupled to the first portion of the second conductive layer and the other end of the second conductive layer. In yet another aspect, the present disclosure provides an apparatus comprising a first capacitor coupled to a first power line, a second capacitor coupled to a second power line, and an intermediate line configured to couple the first capacitor to the second capacitor, wherein the first and second power lines and the intermediate line are contained in a layer. Drawings Fig. 1 is a diagram of a layout of a semiconductor device according to an embodiment of the present disclosure. Fig. 2 is a circuit diagram of a portion of a semiconductor device including a capacitor according to an embodiment of the present disclosure. Fig. 3 is a diagram of a capacitor in a semiconductor device according to an embodiment of the present disclosure. Fig. 4 is a diagram of a layout of a logic circuit block including a capacitor in a semiconductor device according to an embodiment of the present disclosure. Fig. 5 is a circuit diagram of a portion of a semiconductor device incl