CN-115050407-B - Storage device

Abstract

The embodiment provides a memory device capable of reliably performing a read operation. According to one embodiment, a memory device includes a first interconnect, a second interconnect, a memory cell connected between the first interconnect and the second interconnect and including a variable resistive element and a switching element connected in series to the variable resistive element, and a control circuit configured to perform control of a read operation of reading data stored in the memory cell. The control circuit performs control in such a manner that a first interconnect that has been charged with a first voltage and a second interconnect that has been charged with a second voltage are set to a floating state, a switching element is set to an on state by discharging the second interconnect that has been set to the floating state, thereby increasing a voltage applied to the memory cell, and data stored in the memory cell is read in a state in which the switching element is set to the on state.

Inventors

• KATAYAMA AKIRA
• Hatsuda Yukihiro

Assignees

• 铠侠股份有限公司

Dates

Publication Date

20260512

Application Date

20220125

Priority Date

20210309

Claims (20)

1. 1. A storage device, comprising: a first interconnect extending in a first direction; A second interconnect extending in a second direction intersecting the first direction; A memory cell connected between the first interconnect and the second interconnect and including a variable resistance memory element and a switching element connected in series with the variable resistance memory element between a first terminal and a second terminal of the memory cell, the first terminal and the second terminal being connected to the first interconnect and the second interconnect, respectively, and A control circuit configured to perform control of a read operation of reading data stored in the memory cell, wherein, The control circuit performs the control of the read operation in such a manner that: the first interconnect that has been charged with a first voltage and the second interconnect that has been charged with a second voltage are set to a floating state, Setting the switching element to an on state by discharging the second interconnect after the first interconnect and the second interconnect have been set to the floating state, thereby increasing a voltage applied to the memory cell, and The data stored in the memory cell is read by sensing a holding current constantly passing through the memory cell in a state where the switching element is set to the on state and after a voltage applied to the memory cell is reduced from a threshold voltage, which is lower than the threshold voltage and higher than a zero voltage, to a holding voltage.
2. 2. The storage device of claim 1, wherein, When the voltage applied to the memory cell is lower than the holding voltage, the switching element is switched to an off state.
3. 3. The memory device of claim 2, wherein a difference between the first voltage and the second voltage is less than the threshold voltage.
4. 4. The memory device according to claim 2, wherein a difference between a voltage applied to the first interconnect and a voltage applied to the second interconnect is equal to the holding voltage when reading data stored in the memory cell.
5. 5. The memory device of claim 1, wherein the first voltage is equal to the second voltage.
6. 6. The memory device of claim 1, wherein the first voltage is different from the second voltage.
7. 7. The memory device according to claim 1, wherein the control circuit performs control in such a manner that an on-current continuously passes through the switching element after the switching element is set to the on-state.
8. 8. The storage device of claim 7, further comprising: and a constant current source that supplies the on current to the switching element.
9. 9. The storage device of claim 1, further comprising: And a detection circuit that detects a resistance state of the variable-resistance memory element based on an on-current passing through the switching element.
10. 10. The memory device according to claim 9, wherein the detection circuit detects a resistance state of the variable-resistance memory element in a state in which the on-current is held at a constant value.
11. 11. The memory device according to claim 1, wherein the variable resistance memory element is a magnetoresistance effect element.
12. 12. A storage device, comprising: A plurality of bit lines including a first bit line and a second bit line; A plurality of word lines including a first word line and a second word line; A plurality of memory cells between the bit lines and the word lines, each of the memory cells including a variable resistance element and a switching element, the variable resistance element and the switching element being connected in series between a first terminal connected to one of the bit lines and a second terminal connected to one of the word lines; Control circuit, and A detection circuit, wherein, During a read operation that reads data stored in a target memory cell, wherein the target memory cell is one of the memory cells between the first bit line and the first word line, When the first bit line is at a first voltage and the first word line is at a second voltage, the control circuit sets the first bit line and the first word line to a floating state, After setting the first bit line and the first word line to a floating state, the control circuit discharges the first bit line and supplies a constant current to the switching element of the target memory cell to turn on the switching element of the target memory cell, and After a voltage difference between the first word line and the first bit line decreases from a threshold voltage to a holding voltage, which is smaller than the threshold voltage and larger than zero voltage, and a holding current constantly passes through the target memory cell having the switching element in an on state, the detection circuit detects a current passing through the target memory cell and determines data stored in the target memory cell based on the detected current.
13. 13. The memory device according to claim 12, wherein the switching element is switched to an off state when a voltage applied to the memory cell is lower than the holding voltage.
14. 14. The memory device of claim 13, wherein a difference between the first voltage and the second voltage is less than the threshold voltage.
15. 15. The memory device of claim 12, wherein the first voltage is equal to the second voltage.
16. 16. The memory device of claim 12, wherein the first voltage is different from the second voltage.
17. 17. The memory device according to claim 12, wherein the control circuit continuously supplies the current to the switching element after the switching element is turned on.
18. 18. The memory device of claim 12, wherein the detection circuit determines that data having a first value is stored in the target memory cell when the detected current is above a reference level, and the detection circuit determines that data having a second value is stored in the target memory cell when the detected current is below the reference level.
19. 19. The memory device of claim 12, wherein a fixed voltage is applied to the second bit line and the second word line during a read operation of the target memory cell.
20. 20. The memory device of claim 19, wherein the fixed voltage is equal to half the first voltage.

Description

Storage device Cross Reference to Related Applications The present application is based on and claims the priority of Japanese patent application No.2021-037466 filed on 3/9 of 2021 and U.S. patent application No.17/462449 filed on 31 of 2021, the entire contents of which are incorporated herein by reference. Technical Field Embodiments described herein relate generally to storage devices. Background A non-volatile memory device is proposed that comprises memory cells, each comprising a series connection of a variable resistive memory element (such as a magneto-resistive effect element) and a switching element. Disclosure of Invention The embodiment provides a memory device capable of reliably performing a read operation. In general, according to one embodiment, a memory device includes a first interconnect extending in a first direction, a second interconnect extending in a second direction crossing the first direction, a memory cell connected between the first interconnect and the second interconnect and including a variable resistance memory element and a switching element, wherein the switching element is connected in series with the variable resistance memory element between a first end and a second end of the memory cell, the first end and the second end being connected to the first interconnect and the second interconnect, respectively, and a control circuit configured to perform control of a read operation of reading data stored in the memory cell. The control circuit performs control in such a manner that a first interconnect that has been charged with a first voltage and a second interconnect that has been charged with a second voltage are set to a floating state, a switching element is set to an on state by discharging the second interconnect that has been set to the floating state, thereby increasing a voltage applied to the memory cell, and data stored in the memory cell is read in a state in which the switching element is set to the on state. Drawings Fig. 1 is a block diagram showing an overall schematic configuration of a storage device according to an embodiment. Fig. 2A is a perspective view schematically showing the configuration of a memory cell array section in the memory device according to the embodiment. Fig. 2B is a perspective view schematically showing a modified configuration of a memory cell array section in the memory device according to the embodiment. Fig. 3 is a cross-sectional view schematically showing the configuration of a magnetoresistance effect element in a memory device according to an embodiment. Fig. 4 is a cross-sectional view schematically showing the configuration of a selector in a storage device according to an embodiment. Fig. 5 schematically shows the relationship between the voltage applied across the memory cell and the current through the memory cell. Fig. 6 is a circuit diagram illustrating a read operation performed by a memory device according to an embodiment. Fig. 7A to 7C are timing charts showing examples of a read operation performed by the memory device according to the embodiment. Fig. 8A to 8C are timing charts illustrating another example of a read operation performed by a memory device according to an embodiment. Detailed Description Embodiments will be described hereinafter with reference to the drawings. Fig. 1 is a block diagram showing an overall schematic configuration of a storage device (e.g., a nonvolatile storage device) according to an embodiment. Note that a magnetic storage device will be described below as an example of a storage device. The magnetic memory device according to the present embodiment includes a memory cell array section 100, a control circuit 200, and a detection circuit 300. Fig. 2A is a perspective view schematically showing the configuration of the memory cell array section 100. The memory cell array section 100 includes a plurality of word lines (also referred to herein as first interconnections) 10 provided on a base region (not shown, which includes a semiconductor substrate not shown) and extending in an X direction, a plurality of bit lines (also referred to herein as second interconnections) 20 extending in a Y direction, and a plurality of memory cells 30 connected between the plurality of word lines 10 and the plurality of bit lines 20. Note that the X direction, the Y direction, and the Z direction shown in the drawings are directions intersecting each other. More specifically, the X direction, the Y direction, and the Z direction are orthogonal to each other. The word line 10 and the bit line 20 each supply a predetermined signal to each memory cell 30 when writing data to the memory cell 30 or reading data from the memory cell 30. In fig. 2A, although the word line 10 is located at the lower layer side and the bit line 20 is located at the upper layer side, the word line 10 may be located at the upper layer side and the bit line 20 may be located at the lower layer side. Each memory cell 30 includes