CN-115051687-B - Clock generator circuit for generating duty cycle clock signals at low power

Abstract

A clock generator circuit for generating a duty cycle clock signal at low power is disclosed. In one embodiment, an apparatus includes a clock generator circuit to receive a first clock signal at a first frequency and to output a second clock signal at a second frequency that is less than the first clock frequency. The clock generator circuit may include a divider circuit to divide the first clock signal to obtain at least a first divided clock signal and a second divided clock signal, and a gating circuit coupled to the divider circuit to gate the first clock signal with at least one of the first divided clock signal and the second divided clock signal to output the second clock signal.

Inventors

• A.L. Subjects

Assignees

• 硅实验室公司

Dates

Publication Date

20260508

Application Date

20220309

Priority Date

20210309

Claims (19)

1. 1. An apparatus for processing a clock signal, comprising: A clock generator circuit for receiving a first clock signal at a first frequency and outputting a second clock signal at a second frequency less than the first clock frequency, the clock generator circuit comprising: A frequency divider circuit for dividing the first clock signal to obtain at least a first divided clock signal and a second divided clock signal, and A gating circuit coupled to the frequency divider circuit, the gating circuit for gating the first clock signal with at least one of the first divided clock signal and the second divided clock signal to output the second clock signal, and A mixer coupled to the clock generator circuit to down-convert a Radio Frequency (RF) signal using a second clock signal, Wherein the gating circuit comprises a plurality of nand gates, each of the plurality of nand gates for receiving the first clock signal and one of the first divided clock signal or the second divided clock signal.
2. 2. The apparatus of claim 1, wherein the gating circuit is to receive the first clock signal and gate the first clock signal with the first divided clock signal and gate the first clock signal with the second divided clock signal.
3. 3. The apparatus of claim 1, wherein the gating circuit further comprises a plurality of inverters, each inverter of the plurality of inverters coupled to an output of one of the plurality of nand gates.
4. 4. The apparatus of claim 3, wherein each inverter of the plurality of inverters is to output a phase of a second clock signal, the second clock signal comprising a differential quadrature clock signal.
5. 5. The apparatus of claim 3, wherein the gating circuit comprises: A first gated Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and a second gated MOSFET, the first and second gated MOSFETs being gated by a first divided clock signal, the first gated MOSFET having a first terminal coupled to a second terminal of a third MOSFET, and the second gated MOSFET having a first terminal coupled to a first terminal of the third MOSFET, the third MOSFET being gated by the first clock signal.
6. 6. The apparatus of claim 5, wherein the first gated MOSFET has a first aspect ratio and the second gated MOSFET has a second aspect ratio, the first aspect ratio being greater than the second aspect ratio.
7. 7. The apparatus of claim 1, wherein the first divided clock signal and the second divided clock signal comprise strobe signals.
8. 8. The apparatus of claim 7, wherein the width of the second clock signal is defined by the width of the first clock signal, but not by the width of the first divided clock signal or the width of the second divided clock signal.
9. 9. The apparatus of claim 8, wherein an edge rate of the second clock signal is defined by an edge rate of the first clock signal, but not by an edge rate of the first divided clock signal or an edge rate of the second divided clock signal.
10. 10. The apparatus of claim 1, wherein the first divided clock signal has a pulse width that is greater than a pulse width of the first clock signal, and the second clock signal has a pulse width that is at least substantially equal to the pulse width of the first clock signal.
11. 11. The apparatus of claim 1, wherein the clock generator circuit comprises a local oscillator circuit to generate the quadrature 25% duty cycle clock signal comprising the second clock signal.
12. 12. An integrated circuit, comprising: A Low Noise Amplifier (LNA) for receiving and amplifying a Radio Frequency (RF) signal; a mixer coupled to the LNA for down-converting the RF signal to a second frequency signal using a Local Oscillator (LO) clock signal, and A clock generator circuit for receiving a first clock signal at a first frequency and outputting an LO clock signal having a duty cycle that is a fraction of the duty cycle of the first clock signal, the clock generator circuit comprising: A frequency divider circuit for dividing the first clock signal to obtain a plurality of intermediate clock signals, and A gating circuit coupled to the divider circuit, the gating circuit for gating the first clock signal with the plurality of intermediate clock signals to generate the LO clock signal, Wherein the gating circuit comprises a plurality of logic gates, each of the plurality of logic gates receiving a first clock signal and one of the plurality of intermediate clock signals.
13. 13. The integrated circuit of claim 12, wherein the gating circuit further comprises: A plurality of inverters, each of the plurality of inverters coupled to an output of one of the plurality of logic gates.
14. 14. The integrated circuit of claim 13, wherein each of the plurality of inverters is to output a phase of an LO clock signal, the LO clock signal comprising a differential quadrature clock signal.
15. 15. The integrated circuit of claim 12, wherein the clock generator circuit is to generate the LO clock signal having an edge rate defined by an edge rate of the first clock signal and a pulse width at least substantially equal to a pulse width of the first clock signal, the pulse width of the LO clock signal being greater than the pulse width of the plurality of intermediate clock signals.
16. 16. A method for processing a clock signal using the integrated circuit of any one of claims 12 to 15, comprising: receiving an incoming clock signal in a clock generator of the integrated circuit; Clocking a plurality of latches of a divider of a clock generator with an incoming clock signal to generate a plurality of intermediate clock signal phases, and The incoming clock signal is phase-gated with the plurality of intermediate clock signals to generate a Local Oscillator (LO) clock signal from the incoming clock signal, the LO clock signal having a reduced duty cycle relative to the incoming clock signal.
17. 17. The method of claim 16, further comprising outputting the LO clock signal to a mixer of the integrated circuit to down-convert the incoming radio frequency signal to the second frequency signal.
18. 18. The method of claim 16, further comprising: A first latch of the frequency divider is latched with a first phase of the incoming clock signal and a second latch of the frequency divider is latched with a second phase of the incoming clock signal, and The first output signal from the first latch is provided to the input of the second latch and the second output signal from the second latch is provided to the input of the first latch.
19. 19. The method of claim 18, further comprising: Performing a logic operation between the first output signal and a second phase of the incoming clock signal to generate a quadrature phase of the LO clock signal, and A logic operation is performed between the second output signal and the first phase of the incoming clock signal to generate an in-phase of the LO clock signal.

Description

Clock generator circuit for generating duty cycle clock signals at low power Background In many Integrated Circuits (ICs), clock signals for operating components of the IC, including clock signals related to up-conversion and down-conversion of Radio Frequency (RF) signals, are typically generated within the IC itself. Typically, a clock generator receives an incoming clock signal and processes the clock signal to generate a plurality of clock signals having desired properties (such as different frequencies, duty cycles, etc.). In particular, to generate a Local Oscillator (LO) clock signal, careful design of clock generator components is required in which high power consuming, closely matched devices such as various transistors, logic circuits, etc. are used. These components, for example, use relatively large devices to ensure that the clock signal is generated with a desired specification, including having a low phase noise and a high level of matching between quadrature (IQ) signal paths. As such, these clock generators consume relatively high power to output high frequency LO clock signals with low phase noise and high matching levels. Disclosure of Invention In one aspect, an apparatus includes a clock generator circuit to receive a first clock signal at a first frequency and to output a second clock signal at a second frequency that is less than the first clock frequency. The clock generator circuit may include a divider circuit to divide the first clock signal to obtain at least a first divided clock signal and a second divided clock signal, and a gating circuit coupled to the divider circuit to gate the first clock signal with at least one of the first divided clock signal and the second divided clock signal to output the second clock signal. The mixer is coupled to the clock generator circuit to down-convert a Radio Frequency (RF) signal using a second clock signal. In an example, the gating circuit is to receive the first clock signal and gate the first clock signal with the first divided clock signal and gate the first clock signal with the second divided clock signal. The gating circuit may include a plurality of nand gates, each of the plurality of nand gates to receive the first clock signal and one of the first divided clock signal and the second divided clock signal. The gating circuit may further include a plurality of inverters, each of the plurality of inverters coupled to an output of one of the plurality of nand gates. Each of the plurality of inverters outputs a phase of a second clock signal, the second clock signal comprising a differential quadrature clock signal. In an example, the gating circuit includes a first gated Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and a second gated MOSFET, the first gated MOSFET and the second gated MOSFET being gated by a first divided clock signal, the first gated MOSFET having a first terminal coupled to a second terminal of a third MOSFET, and the second gated MOSFET having a first terminal coupled to a first terminal of the third MOSFET, the third MOSFET being gated by the first clock signal. The first gated MOSFET may have a first aspect ratio and the second gated MOSFET may have a second aspect ratio, the first aspect ratio being greater than the second aspect ratio. In an example, the first divided clock signal and the second divided clock signal include strobe signals. The width of the second clock signal is defined by the width of the first clock signal, but not by the width of the first divided clock signal or the width of the second divided clock signal. The edge rate of the second clock signal is defined by the edge rate of the first clock signal, but not by the edge rate of the first divided clock signal or the edge rate of the second divided clock signal. In an example, the pulse width of the first divided clock signal is greater than the pulse width of the first clock signal, and the pulse width of the second clock signal is at least substantially equal to the pulse width of the first clock signal. The clock generator circuit may be a local oscillator circuit to generate a quadrature 25% duty cycle clock signal comprising the second clock signal. In another aspect, a method includes receiving an incoming clock signal in a clock generator of an integrated circuit, clocking a plurality of latches of a divider of the clock generator with the incoming clock signal to generate a plurality of intermediate clock signal phases, and gating the incoming clock signal with the plurality of intermediate clock signal phases to generate a Local Oscillator (LO) clock signal from the incoming clock signal, the LO clock signal having a reduced duty cycle relative to the incoming clock signal. In an example, the method further includes outputting the LO clock signal to a mixer of the integrated circuit to down-convert the incoming radio frequency signal to a second frequency signal. The method may further include latching a first latch