CN-115079996-B - Ultra-high speed pipelined five-point median filtering method based on full parallel hardware logic

CN115079996BCN 115079996 BCN115079996 BCN 115079996BCN-115079996-B

Abstract

The invention discloses a super-high speed pipelined five-point median filtering method based on full parallel hardware logic, which comprises the following steps of S1, caching five-point data of an input one-dimensional signed number sequence x (n), outputting the complement form of the data in parallel with a specific time sequence, S2, preprocessing the parallel data output in S1, S3, parallelizing the preprocessed data in S2 to obtain the size relation between the data, registering the comparison result in a corresponding size relation register, S4, calculating redundancy according to the preprocessed parallel data in S2 and the value of the size relation register in S3 And S5, selecting the index value of the corresponding index number in the original parallel data by using the MUX to output the index value according to the median index number calculated in the S4. The method outputs the median filtering result through fewer comparison times and fewer clock delays, consumes fewer hardware logic resources and has lower calculation delay.

Inventors

HUANG JIYE
XIE HUI
Dong Zhekang
HE ZHIWEI
YANG YUXIANG

Assignees

杭州电子科技大学

Dates

Publication Date: 20260505
Application Date: 20220616

Claims (5)

1. The ultra-high speed pipelined five-point median filtering method based on the full parallel hardware logic is characterized by comprising the following steps: s1, inputting one-dimensional signed number sequence through a data buffer and shaping module Five-point data caching is carried out, and the complement form of the data is transmitted to the first-level streaming module in parallel at a specific time sequence; S2, preprocessing the parallel data output in the S1 through preprocessing logic of a primary pipeline module, wherein the preprocessing comprises data format conversion and data low level supplementation, wherein the method for data low level supplementation comprises the steps of splicing 3bits of redundant bit 001 at the data low level with an index number of 0, splicing 3bits of redundant bit 010 at the data low level with the index number of 1, and so on, and finally obtaining five paths of parallel data; s3, parallelizing the data preprocessed in the S2 by the comparison unit of the first-level pipeline module, obtaining the size relation between each data and other data, and registering the comparison result in a corresponding size relation register; s4, median index judgment logic of the two-stage pipeline module calculates redundancy according to the parallel data preprocessed in S2 and the values of ten size relation registers in S3 Thereby judging the median position and outputting a median index number; The step S4 includes the following sub-steps: S41, classifying ten size relation registers according to whether index values corresponding to index numbers participate in the comparison or not, wherein the registers can be classified into class 1-class 5; s42, carrying out corresponding processing on the register value in each class and accumulating to obtain an accumulated value The processing method for the register value in each class is that if x1 of BT [ x1] [ x2] register in classn is not n, the register value is inverted, if n, no operation is performed; S43, adding up the value And a predetermined threshold value Make difference, make redundancy Calculating, wherein the set threshold T is the median value of index numbers and is set as constant 2; s44, outputting an index number with redundancy of0, namely a median index number; and S5, selecting the index value of the corresponding index number in the original parallel data by using the MUX to output according to the median index number calculated in the S4 by a median selecting unit of the secondary pipeline module.
2. The ultra-high speed pipelined five-point median filtering method based on full parallel hardware logic as recited in claim 1, wherein in step S1, the input one-dimensional signed number sequence is implemented by a register array of N bits in bit width and 5 in length and a counter defined inside the data buffering and shaping module The method includes the steps of carrying out original code to complement combination logic conversion on an input one-dimensional N bits signed number sequence, inputting the converted complement to the register array to carry out shift register on the rising edge of a current clock, carrying out self-adding operation on a counter, repeating the process until the counter count value is 4, resetting the counter in the next clock period, pulling up an output effective signal out_vld, maintaining one clock period and completing data transmission once.
3. The ultra-high speed pipelined five-point median filtering method based on full parallel hardware logic as recited in claim 1, wherein the specific method of step S2 is as follows: S21, judging whether the five paths of parallel data have negative numbers or not when the out_vld of the data caching and shaping module is high, if so, performing the data format conversion, then performing the step S22, and if not, skipping the data format conversion, and directly performing the step S22; S22, carrying out low-order supplementary operation on the data obtained in the step S21, namely supplementing 3bits of redundant bits index+1' b1 on the low order of each path of data according to the data index number index, and outputting five paths of parallel data by the preprocessing logic, wherein the width of the five paths of parallel data is N+3+1 bits.
4. The ultra-high speed pipelined five-point median filtering method based on full parallel hardware logic as claimed in claim 3, wherein in the step S21, the data format conversion method is that the sign bit of five paths of parallel data is subjected to logical OR operation, the logical OR operation result is judged, if the result is "1", the sign bit of each path of data is inverted, the highest bit is filled with 1bit data "0" as the sign bit, and if the result is "0", the step S21 is skipped.
5. The ultra-high speed pipelined five-point median filtering method based on full parallel hardware logic according to claim 1, wherein the parallelization pairwise comparison is performed on the data preprocessed by S2 in S3, and the specific comparison method is as follows: According to the carry-ahead calculation formula: Wherein, the And Is the n-th bit logical value of addends a and B, And As an intermediate variable, the number of the variables, Carry value for low order to home position; Five paths of parallel data are respectively A, B, C, D, E, corresponding index numbers are 0,1, 2, 3 and 4, parallelization is performed on the five paths of parallel data, namely, ten groups of parallel data are calculated for A and-B, A and-C, B and-C, and Cn calculated by each group of data is registered to corresponding size relation registers, wherein the size relation registers are respectively BT01, BT02 and BT12.

Description

Ultra-high speed pipelined five-point median filtering method based on full parallel hardware logic Technical Field The invention relates to the technical field of ultra-high-speed real-time signal processing, in particular to an ultra-high-speed pipelined five-point median filtering method based on full-parallel hardware logic. Background The median filtering is a nonlinear signal processing technology based on a sequencing statistical theory, and the basic principle is that the value of a point in a digital image or a digital sequence is replaced by the median of the values of points in a neighborhood near the point, so that isolated noise points are eliminated, and the filtering purpose is achieved. In the process of realizing the median filtering algorithm by utilizing hardware logic, the calculation of the median value of each window is a core step, and the calculation of the median value occupies most of logic operation time, so that the efficiency of median value calculation determines the running speed of the whole filtering circuit to a great extent. Currently, a median filtering scheme implemented based on an FPGA or an ASIC generally adopts three or more stages of pipelines to perform block comparison on data in a window when calculating a median value, and the scheme consumes a large amount of hardware logic resources and consumes more clock cycles. Disclosure of Invention Aiming at the defects of the prior art, the invention provides a super-high speed pipelined five-point median filtering method based on full-parallel hardware logic, and the median filtering result can be output through fewer comparison times and fewer clock delays. The technical scheme of the invention is as follows: A super-speed pipelined five-point median filtering method based on full parallel hardware logic comprises the following steps: s1, five-point data caching is carried out on an input one-dimensional signed number sequence x (n) through a data caching and shaping module, and the complement form of data is transmitted to a first-level streaming module in parallel according to a specific time sequence; S2, preprocessing the parallel data output in the S1 through preprocessing logic of a primary pipeline module, wherein the preprocessing comprises data format conversion and data low-order supplementation; s3, parallelizing the data preprocessed in the S2 by the comparison unit of the first-level pipeline module, obtaining the size relation between each data and other data, and registering the comparison result in a corresponding size relation register; s4, median index judgment logic of the two-stage pipeline module calculates redundancy according to the parallel data preprocessed in S2 and the values of ten size relation registers in S3 Thereby judging the median position and outputting a median index number; and S5, selecting the index value of the corresponding index number in the original parallel data by using the MUX to output according to the median index number calculated in the S4 by a median selecting unit of the secondary pipeline module. Preferably, in the step S1, five-point data buffering of the input one-dimensional signed number sequence x (N) is implemented through a register array with a bit width of Nbits and a length of 5 and a counter defined in the data buffering and shaping module; the method includes the steps of carrying out original code to complement combination logic conversion on an input one-dimensional N bits signed number sequence, inputting the converted complement to the register array to carry out shift register on the rising edge of a current clock, carrying out self-adding operation on a counter, repeating the process until the counter count value is 4, clearing the counter in the next clock period, pulling up an output effective signal out_vld, maintaining one clock period and completing data transmission once. Preferably, the specific method of the step S2 is as follows: S21, judging whether the five paths of parallel data have negative numbers or not when the out_vld of the data caching and shaping module is high, if so, performing the data format conversion, then performing the step S22, and if not, skipping the data format conversion, and directly performing the step S22; S22, carrying out low-order supplementary operation on the data obtained in the step S21, namely supplementing 3bits of redundant bits index+1' b1 on the low order of each path of data according to the data index number index, and outputting five paths of parallel data by the preprocessing logic, wherein the width of the five paths of parallel data is N+3+1bits. Preferably, in the step S21, the data format conversion method is that the logical OR operation is carried out on the sign bits of the five paths of parallel data, the logical OR operation result is judged, if the result is "1", the sign bit of each path of data is inverted, the highest bit is filled with 1bit data "0" as the sign bit, and if the res