CN-115083458-B - Data storage device and interface circuit thereof

Abstract

The present application relates to a data storage device and an interface circuit therefor. The data storage device may include a memory apparatus including a memory unit for storing data, and an interface circuit coupled between the host apparatus and the memory apparatus as an interface and configured to transmit a transmission signal to the host apparatus. The interface circuit includes a delay circuit configured to generate a delay code and is configured to generate an additional signal to be combined with the transmission signal based on the delay code.

Inventors

• Pei Xianggen

Assignees

• 爱思开海力士有限公司
• 爱思开海力士有限公司

Dates

Publication Date

20260421

Application Date

20211108

Priority Date

20210312

Claims (16)

1. 1. A data storage device storing data under the control of a memory controller of a separate host apparatus, comprising: Memory device including memory cells for storing data, and Interface circuitry coupled between the host device and the memory device as an interface and transmitting a transmission signal to the host device, Wherein the interface circuit comprises a delay circuit generating a delay code, and generating an additional signal to be combined with the transmission signal based on the delay code, Wherein the interface circuit comprises: a pre-emphasis circuit that generates the additional signal by delaying the transmission signal by a delay time determined based on the delay code, and combines the transmission signal and the additional signal.
2. 2. The data storage device of claim 1, wherein the delay time corresponds to one unit interval of the transmission signal, i.e., one UI.
3. 3. The data storage device of claim 1, wherein the interface circuit comprises a plurality of input/output circuits, each input/output circuit comprising the pre-emphasis circuit, and The delay circuit is integrated with the plurality of input/output circuits.
4. 4. The data storage device of claim 1, wherein the delay circuit generates the delay code based on a clock signal used in duty cycle correction after power-up.
5. 5. The data storage device of claim 1, wherein the interface circuit comprises a plurality of input/output circuits, and The delay code is provided to each of the plurality of input/output circuits.
6. 6. The data storage device of claim 1, wherein the pre-emphasis circuit comprises a bypass circuit that receives the transmission data and outputs the corresponding signal without delay, and a further delay circuit that receives the output signal from the delay circuit and outputs the additional signal.
7. 7. A data storage device, comprising: an interface circuit including an input/output control circuit, and A memory device for transmitting data to and receiving data from a host through the interface circuit, Wherein the input/output control circuit includes: A delay circuit for generating an internal clock signal and a delay code based on a clock signal transmitted from the host, and A plurality of input/output circuits, each input/output circuit receiving the delay code and generating an additional signal to be combined with a transmission signal to be transmitted to the host, Wherein each of the plurality of input/output circuits comprises: A pre-emphasis circuit generates the additional signal by delaying the transmission signal by a delay time determined based on the delay code.
8. 8. The data storage device of claim 7, wherein the pre-emphasis circuit comprises a bypass circuit that receives the transmission data and outputs a corresponding signal without delay, and a further delay circuit that receives an output signal from the delay circuit and outputs the additional signal.
9. 9. The data storage device of claim 7, wherein the delay time corresponds to one unit interval of the transmission signal, i.e., one UI.
10. 10. The data storage device of claim 7, wherein the delay circuit is integrated with the plurality of input/output circuits.
11. 11. The data storage device of claim 7, wherein the delay circuit generates the delay code based on a clock signal used in duty cycle correction after power-up.
12. 12. An interface circuit provided in a storage device including a memory device, the interface circuit comprising: a delay circuit for generating an internal clock signal and a delay code based on a clock signal transmitted from a host, and A plurality of input/output circuits, each input/output circuit receiving the delay code and generating an additional signal to be combined with a transmission signal to be transmitted to the host, Wherein each of the plurality of input/output circuits comprises: A pre-emphasis circuit generates the additional signal by delaying the transmission signal by a delay time determined based on the delay code.
13. 13. The interface circuit of claim 12, wherein the pre-emphasis circuit comprises a bypass circuit that receives the transmission data and outputs the corresponding signal without delay, and a further delay circuit that receives the output signal from the delay circuit and outputs the additional signal.
14. 14. The interface circuit of claim 12, wherein the delay time corresponds to one unit interval of the transmission signal, i.e., one UI.
15. 15. The interface circuit of claim 12, wherein the delay circuit is integrated with the plurality of input/output circuits.
16. 16. The interface circuit of claim 12, wherein the delay circuit generates the delay code based on a clock signal used in duty cycle correction after a power-on operation.

Description

Data storage device and interface circuit thereof Cross Reference to Related Applications This patent document claims priority and benefit of korean application No. 10-2021-0032790, filed on 3-12 of 2021, which is incorporated herein by reference in its entirety. Technical Field The technology and embodiments disclosed in this patent document relate generally to a semiconductor integrated device, and more particularly, to a data storage device and an interface circuit thereof. Background The data storage device may include a memory apparatus in which data is stored and a controller that transmits and receives data to and from the memory apparatus in response to a request from a host. The memory device and the controller transmit and receive data through the interface circuit and the channel. Many studies have been made in order to ensure the integrity of data transmitted and received between a memory device and a controller. Disclosure of Invention In an embodiment, a data storage device may include a memory apparatus including a memory unit to store data, and an interface circuit coupled between the host apparatus and the memory apparatus as an interface and configured to transmit a transmission signal to the host apparatus. The interface circuit includes a delay circuit configured to generate a delay code and is configured to generate an additional signal to be combined with the transmission signal based on the delay code. In an embodiment, a data storage device may include an interface circuit including an input/output control circuit, and a memory device configured to transmit data to and receive data from a host through the interface circuit. The input/output control circuit includes a delay circuit configured to generate an internal clock signal and a delay code based on a clock signal transmitted from the host, and a plurality of input/output circuits each configured to receive the delay code and generate an additional signal to be combined with a transmission signal to be transmitted to the host. In an embodiment, an interface circuit, provided in a storage device including a memory device, includes a delay circuit configured to generate an internal clock signal and a delay code based on a clock signal transmitted from a host, and a plurality of input/output circuits, each configured to receive the delay code and generate an additional signal to be combined with a transmission signal to be transmitted to the host. Drawings FIG. 1 is a configuration diagram of a data storage device in accordance with an embodiment of the disclosed technology. Fig. 2 is a configuration diagram of an interface circuit in accordance with an embodiment of the disclosed technology. Fig. 3 is a configuration diagram of a delay locked loop circuit in accordance with an embodiment of the disclosed technology. Fig. 4 is a configuration diagram of an input/output circuit in accordance with an embodiment of the disclosed technology. Fig. 5 is a configuration diagram of a pre-emphasis circuit in accordance with an embodiment of the disclosed technology. Fig. 6A and 6B are waveform diagrams of transmission signals whether to perform pre-emphasis according to the disclosed technology. FIG. 7 is a diagram illustrating a data storage system in accordance with an embodiment of the disclosed technology. Fig. 8 and 9 are diagrams illustrating data processing systems according to embodiments of the disclosed technology. Fig. 10 is a diagram illustrating a network system including a data storage device in accordance with an embodiment of the disclosed technology. FIG. 11 is a block diagram illustrating a non-volatile memory device included in a data storage apparatus in accordance with an embodiment of the disclosed technology. Detailed Description Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. As the capacity and speed of data storage devices increase, the number of unit input/output circuits provided in the interface circuits increases. Accordingly, more studies have been made to accurately and efficiently generate signals to be supplied to each input/output circuit. Fig. 1 is a configuration diagram of a data storage device 10 according to an embodiment. The data storage device 10 may include a host 100 and a storage 200 connected to the host 100 or in communication with the host 100 through a channel 300. The host 100 may include a memory controller 110 for controlling the storage device 200 and a first interface circuit 120 as a host interface circuit if_h. The memory device 200 may include a memory device 210 and a second interface circuit 220 as a memory interface circuit if_d. Host 100 may include a processor and a plurality of IPs (intellectual property cores) operating under the control of the processor. The host 100 may be a system on chip (SoC) in which a plurality of functional blocks, such as IP, that operate various functions are implemented