CN-115083461-B - In-memory computing signal processing circuit

CN115083461BCN 115083461 BCN115083461 BCN 115083461BCN-115083461-B

Abstract

The invention provides an in-memory computing signal processing circuit which comprises N column analog multiply-add units, N current-voltage converter units and a voltage analog-to-digital converter unit, wherein the column analog multiply-add units are used for receiving K input voltages to carry out analog multiply-add operation on the input voltages and weights so as to obtain multiply-add currents, the current-voltage converter units are connected with the column analog multiply-add units in a one-to-one correspondence manner and are used for receiving the multiply-add currents to convert the multiply-add currents into voltage signals, and the voltage analog-to-digital converter units are connected with all the current-voltage converter units and are used for receiving the voltage signals to convert the voltage signals into digital signals.

Inventors

YANG HEYONG
Gao Runxiong
LI CHEN
GUO LINGYI

Assignees

上海集成电路装备材料产业创新中心有限公司
上海集成电路研发中心有限公司

Dates

Publication Date: 20260508
Application Date: 20220627

Claims (9)

1. An in-memory computing signal processing circuit, comprising: The analog multiplying and adding unit comprises K analog multiplying units, a first inverter, a logic operation unit and an output unit, wherein the input end of the latch unit is used for receiving the weight, the output end of the latch unit is connected with the first input end of the logic operation unit, the input end of the first inverter is used for receiving the input voltage, the output end of the first inverter is connected with the second input end of the logic operation unit, the output end of the logic operation unit is connected with the control end of the output unit, and the output end of the output unit outputs the multiplying current; n current-to-voltage converter units connected in one-to-one correspondence with the column analog multiply-add units for receiving the multiply-add current to convert the multiply-add current into a voltage signal, and And the voltage analog-to-digital converter unit is connected with all the current-to-voltage converter units and is used for receiving the voltage signals so as to convert the voltage signals into digital signals.
2. The in-memory computing signal processing circuit of claim 1, wherein the latch unit comprises a first MOS transistor and a latch, a source of the first MOS transistor is configured to receive a weight, a drain of the first MOS transistor is connected to an input of the latch, an output of the latch is connected to a first input of the logic operation unit, and the latch is configured to store the weight.
3. The in-memory computing signal processing circuit of claim 1, wherein the output unit comprises a twelfth MOS transistor, a thirteenth MOS transistor, and a fourteenth MOS transistor, a source of the fourteenth MOS transistor is connected to a power supply negative electrode, a gate of the fourteenth MOS transistor is connected to a bias voltage, a drain of the fourteenth MOS transistor is connected to a source of the thirteenth MOS transistor, a gate of the thirteenth MOS transistor is connected to an output end of the logic operation unit, a drain of the thirteenth MOS transistor is connected to a source of the twelfth MOS transistor, a gate of the twelfth MOS transistor is connected to a preset voltage, and a drain of the twelfth MOS transistor outputs the multiplied current.
4. The in-memory computing signal processing circuit according to claim 1, wherein the current-to-voltage converter unit includes a first voltage input operation unit, a second voltage input operation unit, a third voltage input operation unit, a multiply-add current carrying unit, and an operation result processing unit, the multiply-add current carrying unit being connected to a column analog multiply-add unit, the first voltage input operation unit, the second voltage input operation unit, the third voltage input operation unit for receiving the multiply-add current, the first voltage input operation unit, the second voltage input operation unit, and the third voltage input operation unit for reproducing the multiply-add current in proportion, the operation result processing unit being connected to the first voltage input operation unit, the second voltage input operation unit, the third voltage input operation unit for obtaining the voltage signal based on output currents of the first voltage input operation unit, the second voltage input operation unit, the third voltage input operation unit.
5. The in-memory computing signal processing circuit of claim 4, wherein the multiply-add current carrying unit comprises a fifteenth MOS transistor and a sixteenth MOS transistor, a drain of the fifteenth MOS transistor is connected to the column analog multiply-add unit to receive the multiply-add current, a gate of the fifteenth MOS transistor is connected to a bias voltage, a source of the fifteenth MOS transistor is connected to a drain of the sixteenth MOS transistor and a gate of the sixteenth MOS transistor, and a source of the sixteenth MOS transistor is connected to a power supply anode.
6. The in-memory computing signal processing circuit of claim 5, wherein the first voltage input computing unit, the second voltage input computing unit and the third voltage input computing unit each comprise a first transmission gate, a second transmission gate, a seventeenth MOS transistor, an eighteenth MOS transistor and a nineteenth MOS transistor, an input end of the first transmission gate is connected to a gate of the sixteenth MOS transistor, an output end of the first transmission gate is connected to a gate of the seventeenth MOS transistor and a drain of the eighteenth MOS transistor, a gate of the eighteenth MOS transistor is connected to a control signal, a source of the eighteenth MOS transistor and a source of the seventeenth MOS transistor are both connected to a power supply positive electrode, a drain of the seventeenth MOS transistor is connected to a source of the nineteenth MOS transistor, a gate of the nineteenth MOS transistor is connected to a bias voltage, and a drain of the nineteenth MOS transistor is connected to an input end of the second transmission gate.
7. The in-memory computing signal processing circuit according to claim 6, wherein the operation result processing unit includes a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a capacitor reset unit, and a buffer unit, one end of the first capacitor is connected to an output end of a second transmission gate in the buffer unit, the first voltage input operation unit, one end of the fourth capacitor, and one end of the fifth capacitor, the other end of the fourth capacitor is connected to an output end of a second transmission gate in the second voltage input operation unit, one end of the second capacitor, the other end of the fifth capacitor is connected to an output end of a second transmission gate in the third voltage input operation unit, one end of the third capacitor, the other end of the first capacitor, the other end of the second capacitor, and the other end of the third capacitor are connected to a power supply negative electrode, and the capacitor reset unit is connected to the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, and the fifth capacitor, and the fourth capacitor are used for resetting the first capacitor, the third capacitor, the fourth capacitor, and the fourth capacitor.
8. The in-memory computing signal processing circuit of claim 7, wherein the buffer unit comprises a twentieth MOS transistor and a bias current source, a gate of the twentieth MOS transistor is connected to one end of the first capacitor, a drain of the twentieth MOS transistor is connected to a power supply positive electrode, a source of the twentieth MOS transistor is connected to a positive electrode of the bias current source, a negative electrode of the bias current source is connected to a power supply negative electrode, and a junction between the source of the twentieth MOS transistor and the positive electrode of the bias current source outputs the voltage signal.
9. The in-memory computing signal processing circuit of claim 7, wherein the capacitance resetting unit comprises a twenty-first MOS tube, a twenty-second MOS tube and a twenty-third MOS tube, a drain of the twenty-first MOS tube is connected with one end of the first capacitance, a drain of the twenty-second MOS tube is connected with one end of the second capacitance, a drain of the twenty-third MOS tube is connected with one end of the third capacitance, a gate of the twenty-first MOS tube is connected with a first reset signal, a gate of the twenty-second MOS tube is connected with a second reset signal, a gate of the twenty-third MOS tube is connected with a third reset signal, and a source of the twenty-first MOS tube, a source of the twenty-second MOS tube and a source of the twenty-third MOS tube are connected with a negative electrode of a power supply.

Description

In-memory computing signal processing circuit Technical Field The present invention relates to the field of integrated circuits, and in particular, to an in-memory computing signal processing circuit. Background The von neumann system mechanism is a classical structure of a computer, and the operation principle is that when calculation is needed, data is firstly stored in a storage unit, then the data of the storage unit is carried to a logic unit through an instruction, and after calculation is completed in the logic unit, an operation result is stored in the storage unit. But the data volume becomes larger as the deep learning task. The huge number of parameters makes the traditional von neumann architecture more and more costly in terms of power consumption, latency, etc. to handle large amounts of data between the memory and the CPU, also known as von neumann's memory bottleneck. Therefore, it is necessary to provide a new in-memory computing signal processing circuit to solve the above-mentioned problems in the prior art. Disclosure of Invention The invention aims to provide an in-memory computing signal processing circuit which reduces power consumption and time generated by data carrying. To achieve the above object, the in-memory computing signal processing circuit of the present invention includes: n column analog multiply-add units, each of which is used for receiving K input voltages to perform analog multiply-add operation on the input voltages and weights to obtain multiply-add currents, N and K being natural numbers greater than 0; n current-to-voltage converter units connected in one-to-one correspondence with the column analog multiply-add units for receiving the multiply-add current to convert the multiply-add current into a voltage signal, and And the voltage analog-to-digital converter unit is connected with all the current-to-voltage converter units and is used for receiving the voltage signals so as to convert the voltage signals into digital signals. The in-memory calculation signal processing circuit has the beneficial effects that the in-memory calculation signal processing circuit comprises N column analog multiply-add units, K current-voltage converter units and a voltage analog-to-digital converter unit, realizes an integrated memory calculation function through the circuit, and reduces power consumption and time generated by data carrying. Optionally, the column analog multiplier-adder unit includes K analog multiplier units, where the analog multiplier units include a latch unit, a first inverter, a logic operation unit, and an output unit, an input end of the latch unit is configured to receive the weight, an output end of the latch unit is connected to a first input end of the logic operation unit, an input end of the first inverter is configured to receive an input voltage, an output end of the first inverter is connected to a second input end of the logic operation unit, an output end of the logic operation unit is connected to a control end of the output unit, and an output end of the output unit outputs the multiplication current. Optionally, the latch unit includes a first MOS transistor and a latch, where a source of the first MOS transistor is configured to receive the weight, a drain of the first MOS transistor is connected to an input of the latch, an output of the latch is connected to a first input of the logic operation unit, and the latch is configured to store the weight. Optionally, the output unit includes a twelfth MOS tube, a thirteenth MOS tube and a fourteenth MOS tube, a source electrode of the fourteenth MOS tube is connected to a negative electrode of the power supply, a gate electrode of the fourteenth MOS tube is connected to a bias voltage, a drain electrode of the fourteenth MOS tube is connected to a source electrode of the thirteenth MOS tube, a gate electrode of the thirteenth MOS tube is connected to an output end of the logic operation unit, a drain electrode of the thirteenth MOS tube is connected to a source electrode of the twelfth MOS tube, a gate electrode of the twelfth MOS tube is connected to a preset voltage, and a drain electrode of the twelfth MOS tube outputs the multiplying current. Optionally, the current-to-voltage converter unit includes a first voltage input operation unit, a second voltage input operation unit, a third voltage input operation unit, a multiply-add current carrying unit, and an operation result processing unit, where the multiply-add current carrying unit is connected to the column analog multiply-add unit, the first voltage input operation unit, the second voltage input operation unit, and the third voltage input operation unit, and is configured to receive the multiply-add current, the first voltage input operation unit, the second voltage input operation unit, and the third voltage input operation unit are configured to copy the multiply-add current in proportion, and the operation result processing unit is co