CN-115084141-B - Semiconductor memory device and method of forming the same

Abstract

The present disclosure relates to semiconductor memory devices and methods of forming the same. An apparatus includes a semiconductor substrate, a linear trench in the semiconductor substrate whose inner wall is covered with an insulating film, a first conductive member including a first linear portion and a second linear portion, the first linear portion filling a lower portion of the linear trench, and a linear second conductive member and a linear third conductive member extending along the inner wall of the linear trench and facing each other with a gap therebetween, wherein the second linear portion of the first conductive member protrudes from a central portion of the first linear portion to fill the gap.

Inventors

• Zong Gaoyoumu
• FUJIMOTO TOSHIYASU

Assignees

• 美光科技公司

Dates

Publication Date

20260512

Application Date

20220309

Priority Date

20210316

Claims (20)

1. 1. An apparatus, comprising: a semiconductor substrate; a linear trench in the semiconductor substrate, an inner wall of the linear trench being covered with an insulating film; A first conductive member including a first linear portion and a second linear portion, the first linear portion filling a lower portion of the linear trench; A linear second conductive member and a linear third conductive member extending along opposite portions of the inner wall of the linear groove and facing each other, the linear second conductive member and the linear third conductive member having a gap therebetween, wherein the second linear portion of the first conductive member protrudes from a central portion of the first linear portion to fill the gap, and A cap fill layer is deposited to fill the line-shaped trenches and to cover the top surface of the semiconductor substrate.
2. 2. The apparatus of claim 1, wherein a first work function of the first conductive member is greater than a second work function of the linear second conductive member and the linear third conductive member.
3. 3. The apparatus of claim 1, wherein a first resistance value of the first conductive member is less than a second resistance value of the linear second conductive member and the linear third conductive member.
4. 4. The apparatus of claim 1, wherein the first conductive member comprises titanium nitride.
5. 5. The apparatus of claim 1, wherein the linear second conductive member and the linear third conductive member comprise silicon.
6. 6. The apparatus of claim 1, wherein the linear grooves extend linearly in a predetermined direction.
7. 7. The apparatus of claim 1, wherein the linear second conductive member and the linear third conductive member are disposed on top of the first linear portion, and wherein the linear second conductive member and the linear third conductive member are disposed directly on the insulating film covering respective portions of the inner wall of the linear trench.
8. 8. An apparatus, comprising: a semiconductor substrate; a linear trench in the semiconductor substrate, an inner wall of the linear trench being covered with an insulating film; A first conductive member including a first linear portion and a second linear portion, the first linear portion filling a lower portion of the linear trench and the second linear portion protruding from a central upper surface of the first linear portion, and A linear second conductive member extending between a first portion of the inner wall of the linear trench and the second linear portion of the first conductive member; A linear third conductive member extending between a second portion of the inner wall of the linear groove and the second linear portion of the first conductive member, the second portion of the inner wall being opposite to the first portion of the inner wall, and A cap fill layer is deposited to fill the line-shaped trenches and to cover the top surface of the semiconductor substrate.
9. 9. The apparatus of claim 8, wherein a first work function of the first conductive member is greater than a second work function of the linear second conductive member and the linear third conductive member.
10. 10. The apparatus of claim 8, wherein a first resistance value of the first conductive member is less than a second resistance value of the linear second conductive member and the linear third conductive member.
11. 11. The apparatus of claim 8, wherein the first conductive member comprises titanium nitride.
12. 12. The apparatus of claim 8, wherein the linear second conductive member and the linear third conductive member comprise silicon.
13. 13. The apparatus of claim 8, wherein the linear grooves extend linearly in a predetermined direction.
14. 14. A method, comprising: Forming a linear groove in a substrate; Filling a lower portion of the linear trench with a first conductive member; Covering the surface of the linear trench and the top surface of the first conductive member with a second conductive member; Etching back to remove a portion of the second conductive member covering the top surface of the first conductive member to expose the top surface of the first conductive member, and The gap defined by the remaining second conductive features and the exposed top surface of the first conductive features is filled with a third conductive feature.
15. 15. The method as recited in claim 14, further comprising: the surface of the linear groove is covered with an insulating film, and then the lower portion of the linear groove is filled with the first conductive member.
16. 16. The method as recited in claim 14, further comprising: Etching back the remaining second conductive member and the third conductive member to remove a space of an upper portion of the line-shaped trench.
17. 17. The method as recited in claim 16, further comprising: the space of the upper portion of the line-shaped trench is filled with an insulating film.
18. 18. The method of claim 14, wherein the first conductive member and the third conductive member comprise the same material.
19. 19. The method of claim 18, wherein the first conductive member comprises a different material than the second conductive member.
20. 20. The method of claim 19, wherein a first work function of the first conductive member and the third conductive member is greater than a second work function of the second conductive member.

Description

Semiconductor memory device and method of forming the same Technical Field The present disclosure relates to semiconductor memory devices and methods of forming the same. Background Recently, in a semiconductor memory device such as a dynamic random access memory (hereinafter referred to as DRAM), a trench gate structure is adopted as a structure of a transistor in a memory cell. In a word line having a trench gate structure, a layered structure of titanium nitride (TiN) and polysilicon (poly-Si) is used in a lower portion of a trench. As higher density of the DRAM is further carried out, it is necessary to reduce the resistance of the gate electrode. Disclosure of Invention An aspect of the present disclosure provides an apparatus including a semiconductor substrate, a linear trench in the semiconductor substrate, an inner wall of the linear trench being covered with an insulating film, a first conductive member including a first linear portion and a second linear portion, the first linear portion filling a lower portion of the linear trench, and a linear second conductive member and a linear third conductive member extending along the inner wall of the linear trench and facing each other, the linear second conductive member and the linear third conductive member having a gap therebetween, wherein the second linear portion of the first conductive member protrudes from a central portion of the first linear portion to fill the gap. Another aspect of the present disclosure provides an apparatus including a semiconductor substrate, a line-shaped trench in the semiconductor substrate, an inner wall of the line-shaped trench being covered with an insulating film, a first conductive member including a first line-shaped portion and a second line-shaped portion, the first line-shaped portion filling a lower portion of the line-shaped trench and the second line-shaped portion protruding from a central upper surface of the first line-shaped portion, and a line-shaped second conductive member extending between a portion of the inner wall of the line-shaped trench and the second line-shaped portion of the first conductive member, and a line-shaped third conductive member extending between another portion of the inner wall of the line-shaped trench and the second line-shaped portion of the first conductive member. Another aspect of the present disclosure provides a method including forming a line-shaped trench in a substrate, filling a lower portion of the line-shaped trench with a first conductive feature, covering a surface of the line-shaped trench and a top surface of the first conductive feature with a second conductive feature, etching back to remove a portion of the second conductive feature covering the top surface of the first conductive feature to expose the top surface of the first conductive feature, and filling a gap defined by the remaining second conductive feature and the exposed top surface of the first conductive feature with a third conductive feature. Drawings Fig. 1 is a plan view illustrating a schematic configuration of a portion of a memory cell region of a semiconductor memory device according to an embodiment. Fig. 2 is a plan view illustrating a schematic configuration of a memory tile of a semiconductor memory device according to an embodiment. Fig. 3 is a plan view layout illustrating a schematic configuration of a memory cell region of a semiconductor memory device according to an embodiment. Fig. 4 is a diagram illustrating a method of forming a semiconductor memory device, and is a longitudinal section illustrating a schematic configuration of a memory cell region in an exemplary processing stage, i.e., a longitudinal section illustrating a schematic configuration of a portion along line X-X in fig. 3, according to an embodiment. Fig. 5 is a diagram illustrating a method of forming a semiconductor memory device, and is a longitudinal section illustrating a schematic configuration of a memory cell region in an exemplary processing stage following fig. 4, i.e., illustrating a longitudinal section of a schematic configuration of a portion along line X-X in fig. 3, according to an embodiment. Fig. 6 is a diagram illustrating a method of forming a semiconductor memory device, and is a longitudinal section illustrating a schematic configuration of a memory cell region in an exemplary process stage following fig. 5, i.e., a longitudinal section illustrating a schematic configuration of a portion along line X-X in fig. 3, according to an embodiment. Fig. 7 is a diagram illustrating a method of forming a semiconductor memory device, and is a longitudinal section illustrating a schematic configuration of a memory cell region in an exemplary processing stage following fig. 6, i.e., illustrating a longitudinal section of a schematic configuration of a portion along line X-X in fig. 3, according to an embodiment. Fig. 8 is a diagram illustrating a method of forming a semiconductor memory device, and i