CN-115145860-B - Multi-chip interconnection device, debugging system and debugging method

CN115145860BCN 115145860 BCN115145860 BCN 115145860BCN-115145860-B

Abstract

The application provides a multi-chip interconnection device, a debugging system and a debugging method, wherein the multi-chip interconnection device comprises a circuit board, at least two chips are arranged on the circuit board, and the at least two chips are interconnected through a chip interconnection bus. At least two chips comprise a master chip and other slave chips. An input/output module is arranged in the main chip, and interface pins of the input/output module are led out to the circuit board. The master chip and each slave chip can access the input/output module to output the respective debugging information of each chip through the interface pins in a time-sharing multiplexing mode, so that the execution process debugging information of each chip can be dynamically and effectively obtained in a multi-chip environment. Compared with the prior art that the input and output modules in each chip are led out to the circuit board, the application does not need to lead out the input and output modules in each chip to the circuit board through the interface pins, thereby greatly reducing the number of the interface pins of the input and output modules and wiring and lowering the cost.

Inventors

GONG HAIMING
Du Panyang
ZHANG PANYONG
LI GONGBO

Assignees

成都海光集成电路设计有限公司
成都海光集成电路设计有限公司

Dates

Publication Date: 20260421
Application Date: 20220629
Priority Date: 20220629

Claims (9)

1. A multi-chip interconnect device, comprising: A circuit board; at least two chips arranged on the circuit board and interconnected by a chip interconnection bus, wherein the at least two chips comprise a master chip and other slave chips; an input/output module is arranged in the main chip, and the input/output module is led out to the circuit board through an interface pin arranged on the circuit board; the master chip and each slave chip can access the input and output module so as to output the respective debugging information of each chip through the interface pins in a time-sharing multiplexing mode; the input/output module is internally provided with an identification register, and the identification register is used for being written into a chip logic number which currently has the use right of the input/output module; each chip obtains the chip logic number of the current use right of the input/output module by accessing the identification register; each chip also judges whether the logic number of the chip is equal to the logic number of the chip with the use right of the input/output module, and when the logic numbers are equal, the chip outputs the debug information generated by the chip through the interface pin; Each chip is internally provided with a control module and a computing unit; the computing unit is used for generating debugging information of each chip, the control modules, the input and output modules and the computing units in the master chip are all interconnected through parallel buses, the control modules and the computing units in each slave chip are interconnected through parallel buses, the chip interconnection buses are serial buses, and the control modules in each chip are used for carrying out protocol conversion from the parallel buses to the serial buses.
2. The multi-chip interconnect device of claim 1, wherein the master chip is further configured to write to the identification register a target chip logic number that is required to have access to the input-output module.
3. The multi-chip interconnect device of claim 2, wherein the master chip writes a target chip logic number to the identification register that needs to have access to the input-output module according to a firmware configuration therein.
4. The multi-chip interconnect device of claim 2, wherein the circuit board is further provided with a debug interface; the debugging interface is in communication connection with the main chip so as to input a target chip logic number which needs to have the use right of the input/output module to the main chip, and the main chip writes the received target chip logic number into the identification register.
5. The multi-chip interconnect device of claim 2, wherein the circuit board is further provided with a universal input-output interface; The general input/output interface is in communication connection with the identification register to write a target chip logic number which needs to have the use right of the input/output module into the identification register.
6. The multi-chip interconnect device of claim 5, wherein a configuration select register is also built into the input-output module, the configuration select register communicatively coupled to the universal input-output interface to receive a first configuration instruction and a second configuration instruction; The first configuration instruction is used for configuring the chip logic number which is written into the identification register by the main chip and needs to have the use right of the input/output module, and the second configuration instruction is used for configuring the target chip logic number which is written into the identification register by the general input/output interface and needs to have the use right of the input/output module.
7. A debug system, comprising: A multi-chip interconnect device as claimed in any one of claims 1 to 6; And the debugging device is in communication connection with the interface pin.
8. A method of debugging based on the debugging system of claim 7, comprising: some or all of the at least two chips generate debug information to be output respectively; each chip accesses the input/output module to output the respective debugging information of each chip through the interface pins in a time-sharing multiplexing mode.
9. The debugging method of claim 8, wherein an identification register is built in the input-output module, the identification register is used for being written into a chip logic number currently having the use right of the input-output module; Each chip accesses the input/output module to output the respective debug information of each chip through the interface pins in a time-sharing multiplexing mode, including: Each chip accesses the identification register to acquire the chip logic number of the current use right of the input/output module; Each chip judges whether the logic number of the chip is equal to the logic number of the chip with the use right of the input/output module, and when the logic numbers are equal, the chip outputs the debug information generated by the chip through the interface pin.

Description

Multi-chip interconnection device, debugging system and debugging method Technical Field The present invention relates to the field of semiconductor technologies, and in particular, to a multi-chip interconnection device, a debug system, and a debug method. Background With the increasing demands on the computational performance of processors, processors composed of multi-chip interconnects are becoming increasingly popular. In the process of producing and applying the processor formed by the multi-chip interconnection, the debugging of the processor is an important means for guaranteeing the performance of the processor. In the current debugging design process for the multi-chip interconnection environment, an IO module (input/output module) is usually designed in each chip, the input/output modules in all chips in the multi-chip are connected to a main board through wires and pins, and a debugging interface for pins led out by each chip input/output module is required to be designed on the main board. And when in debugging, obtaining the debugging information of each chip through each debugging interface and pins led out by the corresponding chip input/output module. However, in the application scenario of interconnection of tens of chips, a large number of interface pins and debug interfaces are required in a manner of leading all the interface pins of the input/output modules of all the chips out onto the motherboard and allocating individual debug interfaces, and the cost is extremely high. Disclosure of Invention The invention provides a multi-chip interconnection device, a debugging system and a debugging method, which can dynamically and effectively acquire the debugging information of the execution process of each chip in a multi-chip environment, and the input/output modules in each chip are not required to be led out to a circuit board through interface pins, so that the number and wiring of the interface pins of the input/output modules can be greatly reduced, and the cost is greatly reduced. In a first aspect, the present invention provides a multi-chip interconnect device comprising a circuit board on which at least two chips are disposed, the at least two chips being interconnected by a chip interconnect bus. At least two chips comprise a master chip and other slave chips. The main chip is internally provided with an input/output module, and interface pins of the input/output module are led out to the circuit board. The master chip and each slave chip can access the input/output module to output the respective debugging information of each chip through the interface pins in a time-sharing multiplexing mode. In the scheme, the input/output module in the main chip is led out to the circuit board through the interface pins, each chip can access the input/output module in a multi-chip environment consisting of at least two chips, and the respective debugging information of each chip is output through the interface pins in a time-sharing multiplexing mode among the chips, so that the execution process debugging information of each chip can be dynamically and effectively obtained in the multi-chip environment. Compared with the interconnection mode that the input and output modules in each chip are led out to the circuit board through pins in the prior art, the method does not need to lead out the input and output modules in each chip to the circuit board through interface pins, so that the number of interface pins and wiring of the input and output modules can be greatly reduced, and the cost is greatly reduced. In a specific embodiment, the input/output module is internally provided with an identification register, and the identification register is used for being written into a chip logic number which currently owns the use right of the input/output module. Each chip obtains the chip logic number of the current use right of the input/output module by accessing the identification register. Each chip also judges whether the logic number of the chip is equal to the logic number of the chip with the use right of the input/output module, and when the logic numbers are equal, the debugging information generated by the chip is output through the interface pin. And the method is convenient for informing each chip of which chip the current use right of the input/output module belongs to. In a specific embodiment, the main chip is further configured to write a target chip logic number that needs to possess the usage right of the input/output module into the identification register, so that the target chip logic number is written into the identification register from the chip end, and the usage right of the input/output module is adjusted and allocated. In a specific embodiment, the master chip writes the logic number of the target chip with the use right of the input/output module into the identification register according to the firmware configuration in the master chip, so that the master chip or the sla