CN-115148259-B - Conditional drift-elimination operation of programming memory cells to store data

Abstract

The present disclosure relates to programming memory cells to store conditional drift elimination operations in data. A memory device having a memory cell, a voltage driver, and a controller configured to determine whether to apply a drift-cancel pulse in an opposite polarity of a programming pulse based on a property of the memory cell, the programming pulse configured to place the memory cell in a state representing a data bit. The drift-elimination pulse is skipped if the state of the memory cell is predicted to be insufficient from drift in a previous programming operation to write data into the memory cell to prevent selection of the memory cell during application of the programming pulse. Otherwise, the drift-cancel pulse is applied in the opposite polarity of the program pulse.

Inventors

• WANG HONGMEI
• CUI MINGDONG
• N. N. gajera

Assignees

• 美光科技公司

Dates

Publication Date

20260505

Application Date

20220317

Priority Date

20210330

Claims (20)

1. 1. A method for memory operation, comprising: receiving a command to store a data bit in a memory cell; In response to the command and based on an attribute of the memory cell, deciding whether to apply a drift-cancel pulse to the memory cell before applying a program pulse to the memory cell in a first polarity identified from the data bit, wherein the drift-cancel pulse is in a second polarity opposite the first polarity, and Programming the memory cell to store the data bit according to a result of the determining, wherein the programming comprises: skipping the drift-cancel pulse in response to the result being the first option, or The drift-cancel pulse is applied in response to the result being a second option.
2. 2. The method of claim 1, wherein the memory cell is coupled between two voltage drivers, the first polarity causes current to pass through the memory cell in a first direction, and the second polarity causes current to pass through the memory cell in a second direction opposite the first direction, and the method further comprises: instructing the two voltage drivers to drive a read pulse in the first polarity in response to the result being the first option, and It is determined whether a current through the memory cell during the read pulse has an amplitude greater than a threshold.
3. 3. The method as recited in claim 2, further comprising: the programming pulse is skipped in response to the magnitude of the current through the memory cell exceeding the threshold during the read pulse.
4. 4. The method of claim 2, wherein the voltage driver is configured to drive the read pulse toward a first predefined amplitude and to drive the program pulse toward a second predefined amplitude that is greater than the first predefined amplitude, and the method further comprises: The voltage driver is instructed to switch from driving towards the first predefined amplitude to driving towards the second predefined amplitude without stopping combining the read pulse and the programming pulse.
5. 5. The method of claim 2, wherein the attribute is based at least in part on a location of the memory cell, an address of the memory cell, an electrical distance from the memory cell to the two voltage drivers, or a timing of a command to store data into the memory cell, or any combination thereof.
6. 6. A semiconductor device, comprising: a plurality of memory cells; A plurality of voltage drivers including a first voltage driver connected to a respective memory cell of the plurality of memory cells and a second voltage driver connected to the memory cell, wherein the memory cell is capable of being configured in a first state via the first voltage driver and the second voltage driver driving a first voltage pulse on the memory cell in a first polarity, wherein a voltage driven by the first voltage driver is higher than a voltage driven by the second voltage driver, and And a controller connected to the plurality of voltage drivers, wherein in response to a command configuring the memory cell to have the first state representing storing first data in the memory cell, the controller is configured to determine whether to apply a second voltage pulse on the memory cell in a second polarity opposite to the first polarity based on an attribute of the memory cell, and wherein a voltage driven by the first voltage driver is lower than a voltage driven by the second voltage driver in the second polarity.
7. 7. The semiconductor device of claim 6, wherein the attribute of the memory cell is based at least in part on a location of the memory cell in the semiconductor device.
8. 8. The semiconductor device of claim 6, wherein the attribute of the memory cell is based at least in part on an address of the memory cell in the semiconductor device.
9. 9. The semiconductor device of claim 6, wherein the attribute of the memory cell is based at least in part on an indicator of an electrical distance from the memory cell to the first voltage driver and the second voltage driver.
10. 10. The semiconductor device of claim 6, wherein the attribute of the memory cell is based on a time range in which the memory cell previously applied a voltage pulse to store data.
11. 11. The semiconductor device of claim 6, wherein in response to the first state being a preselected state, the controller is further configured to determine whether to apply the second voltage pulse.
12. 12. The semiconductor device of claim 11, wherein in response to the first state being an alternate state other than the preselected state, the controller instructs the first voltage driver and the second voltage driver to apply the second voltage pulse without determining whether to apply the second voltage pulse based on the attribute.
13. 13. The semiconductor device of claim 12, wherein in the first polarity the first voltage driver is configured to drive a positive voltage relative to ground and the second voltage driver is configured to drive a negative voltage relative to ground, in the second polarity the first voltage driver is configured to drive a negative voltage relative to ground and the second voltage driver is configured to drive a positive voltage relative to ground, upon driving the first voltage pulse the first voltage driver and the second voltage driver are configured to drive a voltage to a first predetermined magnitude, and upon driving the second voltage pulse the first voltage driver and the second voltage driver are configured to drive a voltage to the first predetermined magnitude when the first state is the preselected state.
14. 14. The semiconductor device of claim 13, wherein in response to determining to skip the second voltage pulse, the controller is further configured to instruct the first voltage driver and the second voltage driver to a third voltage pulse in the first polarity and to determine whether a current above a threshold passes through the memory cell during the third voltage pulse.
15. 15. The semiconductor device of claim 14, wherein in response to the current being above the threshold during the third voltage pulse, the semiconductor device is configured to skip the first voltage pulse after the third voltage pulse.
16. 16. The semiconductor device of claim 14, wherein upon driving the third voltage pulse, the first voltage driver and the second voltage driver are configured to drive a voltage to a second predetermined magnitude that is lower than the first predetermined magnitude, and in response to the current being lower than the threshold during the third voltage pulse, the controller is further configured to instruct the first voltage driver and the second voltage driver to change from driving a voltage to the second predetermined magnitude to driving a voltage to the first predetermined magnitude without stopping driving the voltage.
17. 17. An integrated circuit, comprising: A plurality of bit line layers; a plurality of word line layers; A stack of a plurality of memory cells arranged in an array, each of the stack being between a bit line layer of the plurality of bit line layers and a word line layer of the plurality of word line layers, each of the bit line layers being connected to a row of memory cells in the array and each of the word line layers being connected to a column of memory cells in the array; a bit line driver connected to the plurality of bit line layers; A word line driver connected to the plurality of word line layers, wherein each respective memory cell in the stack is connected to a bit line driver and a word line driver, wherein the bit line driver and the word line driver are configured to apply a voltage in a positive polarity when a voltage driven by the bit line driver is higher than a voltage driven by the word line driver and to apply a voltage in a negative polarity when the voltage driven by the bit line driver is lower than the voltage driven by the word line driver, and A controller having a drift predictor configured to predict whether the memory cell has a drift in a current state of the memory cell based on an attribute of the memory cell, the drift being sufficient to prevent the memory cell from being selected during application of a programming pulse by the bit line driver and the word line driver in a first polarity identified by a data bit to be stored in the memory cell; Wherein in response to the drift predictor determining that the drift is sufficient to prevent the memory cell from being selected during the programming pulse, the controller is configured to instruct the bit line driver and the word line driver to apply a drift-cancel pulse in a second polarity opposite the first polarity prior to applying the programming pulse in the first polarity.
18. 18. The integrated circuit of claim 17, wherein the attribute is based at least in part on identifying a stack in which the memory cell is configured, an electrical distance from the memory cell to the bit line driver and the word line driver, or a time of a previous write operation performed for the memory cell, or any combination thereof.
19. 19. The integrated circuit of claim 18, wherein the memory cell has elements that function as both a selector device and a memory device.
20. 20. The integrated circuit of claim 19, wherein the memory cell is selected during the programming pulse when the programming pulse causes the memory cell to become conductive and allows more than a threshold amount of current to pass through the memory cell, and Wherein in response to the drift predictor determining that the drift is insufficient to prevent the memory cell from being selected during the programming pulse, the bit line driver and the word line driver are configured to skip application of the drift-cancel pulse in the opposite second polarity.

Description

Conditional drift-elimination operation of programming memory cells to store data Technical Field At least some embodiments disclosed herein relate generally to programming memory cells to store data and, more particularly, but not by way of limitation, to reducing energy consumption when programming memory cells. Background A memory integrated circuit may have one or more arrays of memory cells formed on an integrated circuit die of semiconductor material. A memory cell is the smallest unit of memory that can be used individually or operated on to store data. In general, a memory cell may store one or more bits of data. Different types of memory cells have been developed for memory integrated circuits, such as Random Access Memory (RAM), read Only Memory (ROM), dynamic Random Access Memory (DRAM), static Random Access Memory (SRAM), synchronous Dynamic Random Access Memory (SDRAM), phase Change Memory (PCM), magnetic Random Access Memory (MRAM), NOR (flash memory), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory, and the like. Some integrated circuit memory cells are volatile and require power to maintain the data stored in the cell. Examples of volatile memory include Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). Some integrated circuit memory cells are non-volatile and can retain stored data even when unpowered. Examples of nonvolatile memory include flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and the like. Flash memory includes NAND (NAND) type flash memory or NOR (NOR) type flash memory. The NAND memory cells are based on NAND logic gates, and the NOR memory cells are based on NOR logic gates. Cross point memory (e.g., 3D XPoint memory) uses an array of non-volatile memory cells. The memory cells in the cross-point memory are transistor-less. Each of such memory cells may have a phase change memory device and a selector device stacked together as columns in an integrated circuit. The memory cells of these columns are connected in an integrated circuit via two layers of wires extending in directions perpendicular to each other. One of the two layers is above the memory cell and the other layer is below the column of memory elements. Thus, each memory cell can be individually selected at the intersection of one wire on each of the two layers. The cross-point memory device is fast and non-volatile and can be used as a general memory pool for processing and storage. During a program/write operation, nonvolatile integrated circuit memory cells can be programmed to store data by applying a voltage or pattern of voltages to the memory cells. The program/write operation sets the memory cell in a state corresponding to the data being programmed/stored into the memory cell. The data stored in the memory cells may be retrieved in a read operation by checking the state of the memory cells. The read operation determines the state of the memory cell by applying a voltage and determining whether the memory cell becomes conductive at the voltage corresponding to the predefined state. Disclosure of Invention In one aspect, this disclosure provides a method comprising receiving a command to store a data bit in a memory cell, determining, in response to the command and based on an attribute of the memory cell, whether to apply a drift-cancel pulse to the memory cell prior to applying a program pulse to the memory cell in a first polarity identified from the data bit, wherein the drift-cancel pulse is in a second polarity opposite the first polarity, and programming the memory cell to store the data bit in accordance with a result of the determining, wherein the programming comprises skipping the voltage-cancel pulse in response to the result being the first option, or applying the voltage-cancel pulse in response to the result being the second option. In another aspect, the present disclosure provides a device comprising a plurality of memory cells, a plurality of voltage drivers including a first voltage driver connected to a respective memory cell of the plurality of memory cells and a second voltage driver connected to the memory cell, wherein the memory cell is capable of being configured in a first state via the first voltage driver and the second voltage driver driving first voltage pulses across the memory cell in a first polarity, wherein a voltage driven by the first voltage driver is higher than a voltage driven by the second voltage driver, and a controller connected to the plurality of voltage drivers, wherein in response to a command configuring the memory cell to have a first state representing storing first data in the memory cell, the controller is configured to determine whether to apply the second voltage pulses across the memory cell in a second polarity opposite the first polarity based on an attribute of