CN-115148669-B - Semiconductor structure and manufacturing method thereof

Abstract

A semiconductor structure is provided. The semiconductor structure may include a transistor structure that may include a gate region disposed above an upper surface of a substrate and extending substantially in a first direction perpendicular to the upper surface of the substrate, a first source/drain region above the upper surface of the substrate, a second source/drain region above the upper surface of the substrate, and a channel region extending vertically in the first direction between the first source/drain region and the second source/drain region, wherein the channel region comprises an oxide semiconductor material. The gate region covers sidewalls of the channel region in a first direction. Embodiments of the present application also relate to methods of fabricating semiconductor structures.

Inventors

• XIE YOUGANG
• JIANG HUIRU
• LIN ZHONGDE

Assignees

• 台湾积体电路制造股份有限公司

Dates

Publication Date

20260512

Application Date

20220126

Priority Date

20210716

Claims (20)

1. 1. A semiconductor structure, comprising: A transistor structure comprising: A gate region disposed above an upper surface of a substrate, wherein the gate region extends substantially in a first direction perpendicular to the upper surface of the substrate; a first source/drain region located above the upper surface of the substrate; A second source/drain region above the upper surface of the substrate, and A channel region laterally between an outermost edge of the first source/drain region and an outermost sidewall of the gate region facing the channel region, wherein the channel region extends vertically in the first direction between the first source/drain region and the second source/drain region, wherein the channel region comprises an oxide semiconductor material; Wherein, along the first direction, the gate region covers sidewalls of the channel region.
2. 2. The semiconductor structure of claim 1, wherein the oxide semiconductor material comprises at least one of indium tin oxide, indium tungsten oxide, indium gallium zinc oxide, titanium oxide, or I x G y Z z MO, wherein M comprises at least one of titanium, aluminum, cerium, or tin, and wherein x, y, and z are each greater than 0 and less than 1.
3. 3. The semiconductor structure of claim 1, wherein the gate region comprises at least one of titanium nitride, tungsten, or molybdenum.
4. 4. The semiconductor structure of claim 1, wherein: along the first direction, the first source/drain region is located between the substrate and the second source/drain region; the first source/drain region has a bottom surface that is closer to the substrate than a bottom surface of the channel region.
5. 5. The semiconductor structure of claim 1, wherein: along the first direction, the first source/drain region is located between the substrate and the second source/drain region; the second source/drain region extends in the first direction across an uppermost surface of the channel region.
6. 6. The semiconductor structure of claim 1, wherein: the transistor structure is a first transistor structure, The semiconductor structure further includes a second transistor structure, the second transistor structure including: A second gate region extending substantially in the first direction; a second channel region extending substantially in the first direction, wherein the second channel region comprises an oxide semiconductor material; Third source/drain region, and A fourth source/drain region; Wherein the second gate region covers substantially the entire second channel region along the first direction, and The gate region of the first transistor structure is electrically connected to the second gate region of the second transistor structure.
7. 7. The semiconductor structure of claim 6, further comprising a word line, wherein the gate region of the first transistor structure and the second gate region of the second transistor structure are part of the word line.
8. 8. The semiconductor structure of claim 1, wherein the transistor structure further comprises: An additional channel region extending substantially in the first direction, wherein the additional channel region comprises an oxide semiconductor material; Third source/drain region, and A fourth source/drain region; Wherein, along the first direction, the gate region covers substantially the entire additional channel region; Wherein the first source/drain region and the second source/drain region are in contact with the channel region; Wherein the third source/drain region and the fourth source/drain region are in contact with the additional channel region.
9. 9. The semiconductor structure of claim 8, wherein the first and second source/drain regions are located on a first side of the gate region, wherein the third and fourth source/drain regions are located on an opposite second side of the gate region.
10. 10. The semiconductor structure of claim 8, wherein the first and second source/drain regions are separated from the third and fourth source/drain regions by the gate region in plan view.
11. 11. The semiconductor structure of claim 8, wherein the first source/drain region, the second source/drain region, the third source/drain region, and the fourth source/drain region form a transistor pair that shares the gate region.
12. 12. A semiconductor structure, comprising: A first transistor structure and a second transistor structure, respectively comprising: A gate region disposed above an upper surface of a substrate and extending substantially in a first direction perpendicular to the upper surface of the substrate; a first source/drain region; Second source/drain region, and A channel region extending substantially in the first direction between the first source/drain region and the second source/drain region, wherein the channel region comprises an oxide semiconductor material; wherein, along the first direction, the gate region of the first transistor structure substantially covers a first sidewall of the channel region of the first transistor structure, Wherein, along the first direction, the gate region of the second transistor structure substantially covers a second sidewall of the channel region of the second transistor structure, Wherein the gate region of the first transistor structure is electrically isolated from the gate region of the second transistor structure; wherein the gate region of the first transistor structure and the gate region of the second transistor structure are located between the first source/drain region of the first transistor structure and the first source/drain region of the second transistor structure.
13. 13. The semiconductor structure of claim 12, wherein the gate region of the first transistor structure and the gate region of the second transistor structure are located between the second source/drain region of the first transistor structure and the second source/drain region of the second transistor structure.
14. 14. The semiconductor structure of claim 12, wherein the gate region of the first transistor structure and the gate region of the second transistor structure have substantially the same length along the first direction.
15. 15. A method of fabricating a semiconductor structure, comprising: forming a first source/drain region; Forming a first dielectric layer over the first source/drain regions; Forming a first recess by removing a portion of the first dielectric layer that does not substantially cover the first source/drain regions; Forming a channel region in the first groove; Forming a gate dielectric region in the first recess in contact with the channel region; filling the first recess with a second dielectric material; forming a second recess by removing a portion of the second dielectric material and exposing the gate dielectric region; Filling the second groove to form a gate region; forming a second dielectric layer over the first dielectric layer and the gate region; Removing portions of the second dielectric layer and the first dielectric layer to expose the channel region, and A second source/drain region is formed in contact with the channel region, wherein the channel region is laterally between an outermost edge of the first source/drain region and an outermost sidewall of the gate region facing the channel region.
16. 16. The method of claim 15, wherein forming the channel region in the first recess comprises depositing an oxide semiconductor material.
17. 17. The method of claim 16, wherein forming the channel region in the first recess comprises anisotropically etching the oxide semiconductor material.
18. 18. The method of claim 16, wherein forming the gate dielectric region in contact with the channel region in the first recess comprises depositing a gate dielectric material.
19. 19. The method of claim 18, wherein the gate dielectric material comprises a high-k dielectric material.
20. 20. The method of claim 18, wherein forming the gate dielectric region in contact with the channel region in the first recess comprises anisotropically etching the gate dielectric material.

Description

Semiconductor structure and manufacturing method thereof Technical Field Embodiments of the present application relate to semiconductor structures and methods of fabricating the same. Background As technology advances, the minimum size of circuit elements that can be fabricated in Integrated Chips (ICs) is continually decreasing. Thus, there is an increasing demand for increasing the number of circuit elements in ICs of the same or smaller size. One way to increase the density of circuit elements in an IC is to fabricate the circuit elements in multiple layers of the IC. Disclosure of Invention Some embodiments of the present application provide a semiconductor structure comprising a transistor structure comprising a gate region disposed above an upper surface of a substrate, wherein the gate region extends substantially in a first direction perpendicular to the upper surface of the substrate, a first source/drain region located above the upper surface of the substrate, a second source/drain region located above the upper surface of the substrate, and a channel region extending vertically in the first direction between the first source/drain region and the second source/drain region, wherein the channel region comprises an oxide semiconductor material, wherein the gate region covers sidewalls of the channel region along the first direction. Further embodiments of the present application provide a semiconductor structure comprising a first transistor structure and a second transistor structure, respectively, comprising a gate region disposed above an upper surface of a substrate and extending substantially in a first direction perpendicular to the upper surface of the substrate, a first source/drain region, a second source/drain region, and a channel region extending substantially in the first direction between the first source/drain region and the second source/drain region, wherein the channel region comprises an oxide semiconductor material, wherein in the first direction the gate region of the first transistor structure substantially covers a first sidewall of the channel region of the first transistor structure, wherein in the first direction the gate region of the second transistor structure substantially covers a second sidewall of the channel region of the second transistor structure, wherein the gate region of the first transistor structure is electrically isolated from the gate region of the second transistor structure, wherein the gate region of the first transistor structure is located between the first gate region and the drain region of the first transistor structure. Still further embodiments of the present application provide a method of fabricating a semiconductor structure comprising forming a first source/drain region, forming a first dielectric layer over the first source/drain region, forming a first recess by removing a portion of the first dielectric layer that does not substantially cover the first source/drain region, forming a channel region in the first recess, forming a gate dielectric region in the first recess that contacts the channel region, filling the first recess with a second dielectric material, forming a second recess by removing a portion of the second dielectric material and exposing the gate dielectric region, filling the second recess to form a gate region, forming a second dielectric layer over the first dielectric layer and the gate region, removing a portion of the second dielectric layer and the first dielectric layer to expose the channel region, and forming a second source/drain region that contacts the channel region. Drawings Aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawing figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Fig. 1A-1D illustrate several schematic diagrams of exemplary transistor structures according to some embodiments of the invention. Fig. 2A to 2B, 3A to 3B, 4A to 4B, 5A to 5B, 6A to 6B, 7A to 7B, 8A to 8B, 9A to 9B, 10A to 10B, 11A to 11B, 12A to 12B, 13A to 13B, 14A to 14B, 15A to 15B, 16A to 16C, 17A to 17C, 18A to 18C, 19A to 19B, 20A to 20B, 21A to 21B, 22A to 22B, 23A to 23B, 24A to 24B, and 25A to 25B illustrate semiconductor structures for explaining exemplary steps for fabricating transistor structures according to some embodiments of the present invention. Fig. 26A and 26B illustrate exemplary dimensions of various structural components of a transistor structure according to some embodiments of the invention. Fig. 27A illustrates a schematic diagram of an exemplary transistor structure array in accordance with some embodiments of the invention. Fig. 27B (including portions (a) and (B)) shows a schematic diagram of a memory array according to some emb