CN-115148782-B - Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure includes providing a substrate, forming an isolation structure on a substrate exposed out of a fin portion, forming a well region injection on the fin portion after the isolation structure is formed, etching back the isolation structure with partial thickness to expose a part of side wall of the fin portion after the well region injection is carried out, and carrying out an annealing process after the well region injection on the fin portion after the isolation structure with partial thickness is etched back. The probability of dislocation defect formation in the annealing process due to lattice damage is reduced, so that the electrical performance of the semiconductor structure is improved.

Inventors

• CAI GUOHUI

Assignees

• 中芯国际集成电路制造(上海)有限公司
• 中芯国际集成电路制造(北京)有限公司

Dates

Publication Date

20260505

Application Date

20210331

Claims (15)

1. 1. A method of forming a semiconductor structure, comprising: Providing a substrate, wherein the substrate comprises a substrate and discrete fin parts positioned on the substrate, and a fin part mask layer is formed on the top of each fin part; Forming an isolation structure on the substrate exposed by the fin part, wherein the isolation structure covers the fin part and the side wall of the fin part mask layer; removing the fin mask layer at the top of the fin; After removing the fin mask layer, carrying out well region injection on the fin; After the well region is implanted, etching back the isolation structure with partial thickness to expose partial side walls of the fin part; forming a protective layer on the side wall and the top of the fin part exposed by the residual isolation structure; and after the protective layer is formed, carrying out an annealing process after well region injection on the fin part.
2. 2. The method of claim 1, wherein the well implant has preset conditions including one or both of heating the substrate during the implant and a low beam current of less than or equal to 200 μΑ.
3. 3. The method of claim 1, wherein forming the protective layer after etching back a portion of the isolation structure and before performing an anneal process after the well implant comprises forming a protective layer on sidewalls and top of the fin exposed by the remaining isolation structure using a deposition process.
4. 4. The method of claim 1, wherein forming the protective layer after etching back the isolation structure with a partial thickness and before performing an annealing process after the well region implantation comprises performing a surface passivation treatment on the fin portion exposed by the remaining isolation structure with a passivation gas, and forming a protective layer on the sidewalls and the top of the fin portion exposed by the remaining isolation structure.
5. 5. The method of forming a semiconductor structure of claim 1, wherein the post well implant anneal process comprises one or more of a soaking anneal process, a spike anneal process, a millisecond anneal process, and a rapid thermal anneal process.
6. 6. The method of claim 1, wherein the parameters of the post-well implant anneal process comprise a reactive gas comprising one or more of N 2 、H 2 、NH 3 、O 2 and Ar, a process temperature of 500 ℃ to 1400 ℃, a process time of 0.1us to 60s, and a chamber pressure of 0.001torr to 780torr.
7. 7. The method of forming a semiconductor structure of claim 3, wherein the deposition process for forming the protective layer comprises an atomic layer deposition process.
8. 8. The method of forming a semiconductor structure of claim 4, wherein the passivation gas is an oxygen-containing gas.
9. 9. The method of forming a semiconductor structure of claim 4 or 8, wherein the passivation gas comprises one or more of O 2 、N 2 O and H 2 O.
10. 10. The method of claim 4, wherein in the step of performing the surface passivation treatment on the fin portion exposed by the remaining isolation structure, the temperature of the surface passivation treatment is 600 ℃ to 1200 ℃.
11. 11. The method of claim 4, wherein the passivation gas is used in the step of performing the surface passivation treatment on the fin portion exposed by the remaining isolation structure in an amount of greater than 10ppm.
12. 12. The method of forming a semiconductor structure of claim 2, wherein the substrate is heated to a temperature of 50 ℃ to 500 ℃.
13. 13. The method of claim 2, wherein the low beam current has a current value of 20 μΑ to 200 μΑ.
14. 14. The method of forming a semiconductor structure of claim 1, wherein the process of forming the isolation structure comprises fluid chemical vapor deposition.
15. 15. The method of forming a semiconductor structure of claim 1, wherein the process of etching back a portion of the thickness of the isolation structure comprises a dry etching process.

Description

Method for forming semiconductor structure Technical Field The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background In semiconductor manufacturing, with the trend of very large scale integrated circuits, the feature size of integrated circuits is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of Metal-Oxide-semiconductor field effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate structure on the channel is further and further reduced, and the difficulty of pinching off the channel by the gate voltage is further and further increased, so that the phenomenon of subthreshold leakage (subthreshold leakage), namely the so-called short channel effect (SCE: short-CHANNEL EFFECTS), is more likely to occur. Accordingly, to better accommodate the reduction in feature sizes, semiconductor processes are increasingly beginning to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) from at least two sides, compared with a planar MOSFET, the gate structure has stronger control capability on a channel, can well inhibit short channel effect, and has better compatibility with the existing integrated circuit manufacturing compared with other devices. Disclosure of Invention The embodiment of the invention solves the problem of providing a method for forming a semiconductor structure, which is beneficial to improving the electrical performance of the semiconductor structure. In order to solve the problems, the embodiment of the invention provides a method for forming a semiconductor structure, which comprises the steps of providing a substrate, forming an isolation structure on the substrate exposed by a fin portion, forming a well region injection on the fin portion after the isolation structure is formed, etching back the isolation structure with partial thickness to expose partial side wall of the fin portion after the well region injection is performed, and performing an annealing process after the well region injection on the fin portion after the isolation structure with partial thickness is etched back. Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages: The embodiment of the invention provides a method for forming a semiconductor structure, which comprises the steps of forming an isolation structure on a substrate with exposed fin parts, forming the isolation structure to cover the side walls of the fin parts, performing well region injection on the fin parts after forming the isolation structure, etching back the isolation structure with partial thickness after performing the well region injection to expose part of the side walls of the fin parts, and performing an annealing process after the well region injection on the fin parts after etching back the isolation structure with partial thickness. The fin portion is easy to be damaged by crystal lattice in the well region injection process, larger stress is usually generated on the fin portion in the isolation structure forming process, under the condition that internal stress exists, dislocation defects are easy to be formed in the annealing process after the well region injection is carried out subsequently on the fin portion, and because the stress generated by the isolation structure is positively correlated with the size of the fin portion, after the well region injection is carried out on the fin portion, the isolation structure with partial thickness is etched back firstly to achieve the effect of reducing the size of the isolation structure, the influence of the internal stress of the isolation structure on the exposed fin portion is reduced or eliminated, and then when the annealing process after the well region injection is carried out on the fin portion, the probability of forming the dislocation defects in the fin portion is greatly reduced, so that the electrical performance of the semiconductor structure is improved. In an alternative, the well implant has preset conditions including one or both of heating the substrate during the implant and a low beam current of less than or equal to 200 μa. In the process of carrying out well region injection under the preset condition, the kinetic energy of the injected ions and atoms (such as silicon atoms) in the fin material can be increased, so that the injected ions and the atoms in the fin material generate attraction or repulsion force between each other, the atoms in crystal lattices can be rearranged, correspondingly, the probability of lattice damage caused in