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CN-115148786-B - GGNMOS device

CN115148786BCN 115148786 BCN115148786 BCN 115148786BCN-115148786-B

Abstract

The invention provides a GGNMOS device, wherein a first N-type sub-doping layer, a second N-type sub-doping layer and a third N-type sub-doping layer are formed at an N-type well layer, which is equivalent to forming a larger parasitic resistance between the first N-type sub-doping layer and the second N-type sub-doping layer, and the same larger parasitic resistance is formed between the first N-type sub-doping layer and the third N-type sub-doping layer, so that the manufacturing cost of the GGNMOS device is reduced while the high withstand voltage of the drain electrode structure of the GGNMOS device is ensured.

Inventors

  • GUO WENWU
  • CHEN YU
  • JI XIANGYU
  • TAI LIANLIANG
  • LI GUANGREN

Assignees

  • 深圳朗田亩半导体科技有限公司

Dates

Publication Date
20260505
Application Date
20220630

Claims (10)

  1. 1. A GGNMOS device, comprising: A P-type substrate; a gate structure on one side surface of the P-type substrate; The semiconductor device comprises a grid structure, a source electrode structure, a drain electrode structure and a substrate electrode structure, wherein the source electrode structure and the drain electrode structure are respectively positioned at two sides of the grid structure, the substrate electrode structure is positioned at one side of the source electrode structure far away from the grid structure, the drain electrode structure comprises an N-type well layer which is implanted into the P-type substrate, a first N-type sub-doping layer and a second N-type sub-doping layer which are implanted into the N-type well layer, the second N-type sub-doping layer is positioned between the grid structure and the first N-type sub-doping layer, the first N-type sub-doping layer is used for an external terminal, and the doping concentration of the first N-type sub-doping layer and the second N-type sub-doping layer is larger than that of the N-type well layer; in the range area of the N-type well layer, no nonmetallic silicide is isolated at the gap area between the adjacent N-type sub-doped layers, and the gap area between the adjacent N-type sub-doped layers is only a partial structure of the N-type well layer; and in the range area of the N-type well layer, any one side of any N-type sub-doping layer is of a partial structure of the N-type well layer, so that any one side of any N-type sub-doping layer has no P-type structure.
  2. 2. The GGNMOS device of claim 1, wherein a set gap is provided between the N-well layer and the gate structure; the second N-type sub-doping layer covers the set gap and extends to the N-type well layer.
  3. 3. The GGNMOS device of claim 1, wherein the gate structure comprises a gate oxide layer on a side surface of the P-type substrate, and a polysilicon layer on a side of the gate oxide layer facing away from the P-type substrate.
  4. 4. The GGNMOS device of claim 1, in which the source structure comprises an N-doped layer implanted into the P-type substrate.
  5. 5. The GGNMOS device of claim 1, wherein the substrate electrode structure comprises a P-type doped layer implanted into the P-type substrate, the P-type doped layer having a doping concentration greater than a doping concentration of the P-type substrate.
  6. 6. A GGNMOS device, comprising: A P-type substrate; a first gate structure and a second gate structure on one side surface of the P-type substrate; A drain structure between the first gate structure and the second gate structure, a first source structure and a first substrate electrode structure on a side of the first gate structure remote from the drain structure, and a second source structure and a second substrate electrode structure on a side of the second gate structure remote from the drain structure; The drain structure comprises an N-type well layer implanted into the P-type substrate, a first N-type sub-doping layer, a second N-type sub-doping layer and a third N-type sub-doping layer are implanted into the N-type well layer, the first N-type sub-doping layer is positioned between the second N-type sub-doping layer and the third N-type sub-doping layer, the second N-type sub-doping layer is positioned at one side close to the first gate structure, the first N-type sub-doping layer is used for an external terminal, and the doping concentration of the first N-type sub-doping layer, the second N-type sub-doping layer and the third N-type sub-doping layer is larger than that of the N-type well layer; in the range area of the N-type well layer, no nonmetallic silicide is isolated at the gap area between the adjacent N-type sub-doped layers, and the gap area between the adjacent N-type sub-doped layers is only a partial structure of the N-type well layer; and in the range area of the N-type well layer, any one side of any N-type sub-doping layer is of a partial structure of the N-type well layer, so that any one side of any N-type sub-doping layer has no P-type structure.
  7. 7. The GGNMOS device of claim 6, wherein a first set gap is provided between the N-well layer and the first gate structure, and a second set gap is provided between the N-well layer and the second gate structure; The second N-type sub-doping layer covers the first set gap and extends to the N-type well layer, and the third N-type sub-doping layer covers the second set gap and extends to the N-type well layer.
  8. 8. The GGNMOS device of claim 6, wherein either the first gate structure or the second gate structure comprises a gate oxide layer on a side surface of the P-type substrate, and a polysilicon layer on a side of the gate oxide layer facing away from the P-type substrate.
  9. 9. The GGNMOS device of claim 6, in which either of the first source structure and the second source structure comprises an N-doped layer implanted into the P-type substrate.
  10. 10. The GGNMOS device of claim 6, wherein either of the first substrate electrode structure and the second substrate electrode structure comprises a P-type doped layer implanted into the P-type substrate, the P-type doped layer having a doping concentration greater than a doping concentration of the P-type substrate.

Description

GGNMOS device Technical Field The invention relates to the technical field of semiconductors, in particular to a GGNMOS (Gate-Grounded NMOS, gate-grounded N-type metal oxide transistor) device. Background The integrated circuit is easily damaged by static electricity, and the static electricity protection circuit is generally designed at the input and output ends of the circuit or the power protection device to prevent the internal circuit from being damaged due to static electricity. GGNMOS (GateGroundedNMOS, gate grounded N-type metal oxide transistor) is a widely used electrostatic protection structure. The electrostatic protection is carried out through electrostatic discharge, and the mechanism is that the power consumption on the MOS tube is the product of the passing current and the voltage drop, and under certain ESD electrostatic current, if the voltage drop on the MOS tube can be reduced, the power consumption on the MOS tube can be reduced, and then the junction temperature of the MOS tube is reduced, so that the purpose of protecting the MOS tube is achieved. The GGNMOS is used as an ESD device to forward conduct and discharge ESD current by means of a parasitic NPN (N+ active region of a drain electrode-N+ active region of a P-type substrate-source electrode) BJT, and to reverse conduct and discharge ESD current by means of a PN diode (N+ active region of a P-type substrate-drain electrode). In a full-chip ESD network, when an ESD event occurs, both the GGNMOS forward and reverse directions may be turned on, which is determined by the potential ESD path, and ESD current always flows to the low-resistance path. Therefore, the forward and reverse ESD performance of the GGNMOS must be considered in design to absolutely guarantee the reliability of the chip. Normally, the diode has strong forward conduction discharge capability, the P-type substrate of the GGNMOS and the PN junction diode parasitic to the N+ drain electrode can be used as negative-pressure discharge paths, when positive-pressure static electricity exists on the drain electrode, avalanche breakdown can occur on the parasitic PN junction between the drain electrode and the substrate, and then a bipolar NPN parasitic to the GGNMOS can be started to form a low-resistance path to discharge static current. In order to improve the withstand voltage of the drain structure, the conventional GGNMOS device generally forms a non-metal silicide on the drain structure through Salicide Block Mask (silicide film forming process), and the process is complicated because Salicide Block Mask is required for preparing the non-metal silicide, thereby increasing the process and the manufacturing cost of the GGNMOS device. Disclosure of Invention In view of the above, the invention provides a GGNMOS device, which effectively solves the problems existing in the prior art, and reduces the manufacturing cost of the GGNMOS device while ensuring higher withstand voltage of the drain structure of the GGNMOS device. In order to achieve the above purpose, the technical scheme provided by the invention is as follows: a GGNMOS device comprising: A P-type substrate; a gate structure on one side surface of the P-type substrate; The semiconductor device comprises a grid structure, a source electrode structure, a drain electrode structure and a substrate electrode structure, wherein the source electrode structure and the drain electrode structure are respectively arranged at two sides of the grid structure, the substrate electrode structure is arranged at one side of the source electrode structure far away from the grid structure, the drain electrode structure comprises an N-type well layer which is implanted into the P-type substrate, a first N-type sub-doping layer and a second N-type sub-doping layer which are implanted into the N-type well layer, the second N-type sub-doping layer is arranged between the grid structure and the first N-type sub-doping layer, the first N-type sub-doping layer is used for an external terminal, and the doping concentration of the first N-type sub-doping layer and the second N-type sub-doping layer is larger than that of the N-type well layer. Optionally, a set gap is formed between the N-type well layer and the gate structure; the second N-type sub-doping layer covers the set gap and extends to the N-type well layer. Optionally, the gate structure includes a gate oxide layer on a surface of one side of the P-type substrate, and a polysilicon layer on a side of the gate oxide layer facing away from the P-type substrate. Optionally, the source structure includes an N-doped layer implanted into the P-type substrate. Optionally, the substrate electrode structure includes a P-type doped layer implanted into the P-type substrate, and the doping concentration of the P-type doped layer is greater than the doping concentration of the P-type substrate. Correspondingly, the invention also provides a GGNMOS device, which comprises: A P-type substr