CN-115149965-B - Low density parity check LDPC decoder, decoding method and related equipment

Abstract

The embodiment of the application provides an LDPC decoder, a decoding method and related equipment, wherein the decoder comprises an optical chip and an electrical chip, the electrical chip is used for receiving a bit sequence transmitted by a channel, determining first probability information according to the bit sequence and transmitting the first probability information to the optical chip through an electrical signal, the optical chip is used for carrying out multiplication operation on the first probability information to obtain a first multiplication result, the electrical chip is also used for updating a check node according to the first multiplication result to obtain second probability information and transmitting the second probability information to the optical chip through the electrical signal, the optical chip is also used for carrying out multiplication operation on the second probability information to obtain a second multiplication result, the electrical chip is also used for carrying out update on a variable node according to the second multiplication result to obtain third probability information, and the decoding value of the bit sequence is determined according to the third probability information. The embodiment of the application can improve the decoding rate and reduce the power consumption in the decoding process.

Inventors

• XU BO
• LIU CHENG

Assignees

• 华为技术有限公司

Dates

Publication Date

20260512

Application Date

20210331

Claims (20)

1. 1. A low density parity check LDPC decoder is provided, wherein the decoder comprises an optical chip and an electrical chip, the optical chip and the electrical chip being connected, wherein, The electrical chip is used for: Receiving a bit sequence transmitted by a channel, the bit sequence being encoded according to a low density parity check, LDPC, code; Determining first probability information according to the bit sequence, and transmitting the first probability information to the optical chip through an electric signal; The optical chip is used for: Converting the first probability information of the electrical signal into the first probability information of an optical signal; multiplying the first probability information of the optical signal to obtain a first multiplication result; the electrical chip is further used for updating the check node according to the first multiplication result to obtain second probability information, and transmitting the second probability information to the optical chip through an electrical signal; The optical chip is further configured to: Converting the second probability information of the electrical signal into the second probability information of an optical signal; multiplying the second probability information of the optical signal to obtain a second multiplication result; The electrical chip is further configured to: updating the variable nodes according to the second multiplication result to obtain third probability information; and determining a coding value of the bit sequence according to the third probability information.
2. 2. The decoder of claim 1, wherein the electrical chip is further configured to: Multiplying the first probability information by a first preset coefficient, and transmitting the multiplied first probability information to the optical chip through an electric signal; and multiplying the second probability information by a second preset coefficient, and transmitting the multiplied second probability information to the optical chip through an electric signal.
3. 3. Decoder according to claim 2, characterized in that the electrical chip is in particular adapted to: Dividing the first multiplication result by the first preset coefficient, and updating the check node according to the first multiplication result after division operation to obtain the second probability information; dividing the second multiplication result by the second preset coefficient, and updating the variable nodes according to the second multiplication result after division operation to obtain the third probability information.
4. 4. The decoder according to claim 1, wherein the optical chip is specifically configured to: generating a first input optical signal by an optical source; and adjusting the first input optical signal according to the first probability information of the electric signal through an optical multiplier to determine the first probability information of the optical signal.
5. 5. The decoder of claim 4, wherein the optical chip is specifically configured to: determining a first refractive index of the optical multiplier from the first probability information of the electrical signal; The first input optical signal is adjusted according to the first refractive index to determine the first probability information of the optical signal.
6. 6. The decoder according to claim 1, wherein the optical chip is specifically configured to: generating a second input optical signal by the optical source; Adjusting the second input optical signal by an optical multiplier according to the second probability information of the electrical signal to determine the second probability information of the optical signal.
7. 7. The decoder of claim 6, wherein the optical chip is specifically configured to: determining a second refractive index of the optical multiplier based on the second probability information of the electrical signal; the second probability information of the optical signal is determined by adjusting the second input optical signal according to the second refractive index.
8. 8. The decoder of any of claims 4 through 7 wherein the optical multipliers comprise one or more of mach-zehnder interferometers, directional couplers and micro-rings.
9. 9. A low density parity check LDPC decoding method is characterized in that the method is applied to an LDPC decoder, the decoder comprises an optical chip and an electrical chip, the optical chip is connected with the electrical chip, and the method comprises the following steps: receiving, by the electrical chip, a bit sequence transmitted by a receive channel, the bit sequence encoded according to a low density parity check, LDPC, code; Determining first probability information by the electrical chip according to the bit sequence, and transmitting the first probability information to the optical chip by an electrical signal; Converting the first probability information of the electrical signal into the first probability information of an optical signal by the optical chip; multiplying the first probability information of the optical signal by the optical chip to obtain a first multiplication result; updating the check node through the electrical chip according to the first multiplication result to obtain second probability information, and transmitting the second probability information to the optical chip through an electrical signal; converting the second probability information of the electrical signal into the second probability information of an optical signal by the optical chip; multiplying the second probability information of the optical signal by the optical chip to obtain a second multiplication result; Updating the variable nodes through the electric chip according to the second multiplication result to obtain third probability information; and determining, by the electrical chip, the bit sequence decoding value according to the third probability information.
10. 10. The method of claim 9, wherein determining, by the electrical chip, first probability information from the bit sequence and transmitting the first probability information to the optical chip by an electrical signal, comprises: After the first probability information is determined according to the bit sequence through the electric chip, the first probability information is multiplied by a first preset coefficient, and the multiplied first probability information is transmitted to the optical chip through an electric signal.
11. 11. The method of claim 10, wherein updating, by the electrical chip, the check node according to the first multiplication result to obtain second probability information, and transmitting, by an electrical signal, the second probability information to the optical chip, comprises: Dividing the first multiplication result by the first preset coefficient through the electric chip, updating the check node according to the first multiplication result after division operation to obtain the second probability information, and transmitting the second probability information to the optical chip through an electric signal.
12. 12. The method of claim 9, wherein updating, by the electrical chip, the check node according to the first multiplication result to obtain second probability information, and transmitting, by an electrical signal, the second probability information to the optical chip, comprises: And after updating the check node according to the first multiplication result by the electric chip to obtain second probability information, multiplying the second probability information by a second preset coefficient, and transmitting the multiplied second probability information to the optical chip by an electric signal.
13. 13. The method of claim 12, wherein updating, by the electrical chip, the check node according to the second multiplication result to obtain third probability information, comprises: And dividing the second multiplication result by the second preset coefficient through the electric chip, and updating the variable node according to the second multiplication result after division operation to obtain the third probability information.
14. 14. The method of claim 9, wherein the optical chip includes a light source and an optical multiplier, the converting, by the optical chip, the first probability information of the electrical signal into the first probability information of an optical signal, comprising: generating a first input optical signal by an optical source; First probability information for the optical signal is determined by adjusting the first input optical signal by an optical multiplier based on the first probability information for the electrical signal.
15. 15. The method of claim 14, wherein said determining said first probability information for said optical signal by adjusting said first input optical signal by an optical multiplier based on said first probability information for said electrical signal comprises: determining a first refractive index of the optical multiplier from the first probability information of the electrical signal; The first input optical signal is adjusted according to the first refractive index to determine the first probability information of the optical signal.
16. 16. The method of claim 9, wherein the optical chip includes a light source and an optical multiplier, the converting, by the optical chip, the second probability information of the electrical signal into the second probability information of the optical signal, comprising: generating a second input optical signal by the optical source; The second probability information of the optical signal is determined by adjusting the second input optical signal by an optical multiplier according to the second probability information of the electrical signal.
17. 17. The method of claim 16, wherein said determining, by said optical multiplier, said second probability information for said optical signal by adjusting said second input optical signal in accordance with said second probability information for said electrical signal comprises: determining a second refractive index of the optical multiplier based on the second probability information of the electrical signal; the second probability information of the optical signal is determined by adjusting the second input optical signal according to the second refractive index.
18. 18. The method of any of claims 14 to 17, wherein the optical multiplier comprises one or more of a mach-zehnder interferometer, a directional coupler, and a micro-ring.
19. 19. An electronic device comprising a decoder as claimed in any of claims 1 to 8, and a discrete device coupled to the decoder.
20. 20. A computer readable storage medium, characterized in that the computer readable storage medium stores a computer program which, when executed by a processor, implements the method of any of the preceding claims 9-18.

Description

Low density parity check LDPC decoder, decoding method and related equipment Technical Field The present application relates to the field of information processing, and in particular, to an LDPC decoder, a decoding method, and related devices. Background With the development of communication technology, communication systems are moving toward large capacity, high efficiency, and high throughput. But the information may be interfered by noise of the channel during the transmission process, reducing the reliability of the information. Whereas efficiency and reliability are two contradictory properties, for example, the time taken per unit time needs to be shortened if the efficiency of information transmission is to be achieved. Therefore, the energy of the information may be reduced, so that the anti-interference capability of the information in the transmission process is deteriorated, errors are easily generated, and the reliability is reduced. The channel coding can ensure the reliability of information transmission, and as a channel coding method with the performance closest to shannon limit, the Low density parity check (Low DENSITY PARITY CHECK, LDPC) code plays an important role. The LDPC code is a linear block code with a sparse check matrix proposed by Gallager, i.e. only a small number of elements in the check matrix are "1" and most of the elements are "0". The sparsity of the check matrix is utilized, so that the decoding complexity is only in linear relation with the code length, and the decoding process is not excessively complicated under the condition of longer code length. LDPC decoding algorithms are very heterogeneous, since the performance of the belief propagation (Belief Propagation, BP) algorithm can approach shannon's limit, and BP algorithms can be used for decoding in general. However, the BP algorithm of LDPC decoding includes a large number of multiplications, and the chip currently applied to the BP algorithm of LDPC decoding mainly includes a graphics processing unit (GRAPHICAL PROCESSING UNITS, GPUs), a programmable gate array (Field Programmable GATE ARRAYS, FPGAS), and three general types of Application-SPECIFIC INTEGRATED circuits (ASICs) all based on conventional electrical chip technologies. With the slow development of moore's law, the conventional electrical chip technology faces the problems of high power consumption, slow speed and the like, which may result in the reduction of decoding reliability. Disclosure of Invention The embodiment of the application discloses a low-density parity check LDPC decoder, a decoding method and related equipment, which can improve the decoding rate and reduce the power consumption in the decoding process. The embodiment of the application provides a low-density parity check LDPC decoder, which comprises an optical chip and an electrical chip, wherein the optical chip is connected with the electrical chip, the electrical chip is used for receiving a bit sequence transmitted by a channel, the bit sequence is encoded according to the low-density parity check LDPC code, determining first probability information according to the bit sequence and transmitting the first probability information to the optical chip through an electric signal, the optical chip is used for converting the first probability information of the electric signal into the first probability information of the optical signal, multiplying the first probability information of the optical signal to obtain a first multiplication result, the electrical chip is also used for updating a check node according to the first multiplication result to obtain second probability information and transmitting the second probability information to the optical chip through the electric signal, the optical chip is also used for converting the second probability information of the electric signal into the second probability information of the optical signal, obtaining a second multiplication result, the electrical chip is also used for updating a variable node according to the second multiplication result to obtain third probability information, and determining a decoding value of the bit sequence. It can be seen that a large number of multiplications (which may be successive multiplications) may occur due to the LDPC decoding process (e.g., the process of updating check nodes and the process of updating variable nodes). In the embodiment of the application, the optical chip processes multiplication operation in the decoding process, and the electric chip transmits information to the optical chip through the electric signal to control the optical chip, so that the optical chip can obtain a corresponding multiplication result. The optical chip converts the multiplication result obtained by the operation into an electric signal to be transmitted to the electric chip, and the electric chip is used for completing other operations except the multiplication operation in the decoding process. The clo