CN-115168292-B - Impedance test file generation method

Abstract

The invention discloses a method for generating an impedance test file, which comprises the following steps of S1, calling an ERP file and a TGZ file from a database by Genesis software, wherein the ERP file comprises impedance information of a PCB, the TGZ file comprises image layer information of the PCB, S2, identifying a grounding point by the Genesis software according to the TGZ file, S3, identifying a single-ended impedance line and a differential impedance line according to the ERP file, calculating the lengths of the single-ended impedance line and the differential impedance line, S4, locating coordinates of the grounding point and the endpoint of the single-ended impedance line with the length within a preset range and coordinates of the two endpoints of the differential impedance line with the length within the preset range, forming a CSV file by the single-ended impedance line, the differential impedance line and the corresponding coordinates, and S5, decoding the CSV file into a DIF file and outputting the DIF file. The method for generating the impedance test file can automatically output the grounding point and the impedance line, can output all data at one time, and ensures that the impedance test file can be generated quickly and effectively.

Inventors

• ZHOU ZHENHUA
• ZHANG DEJIN
• LI KAI

Assignees

• 广州广合科技股份有限公司

Dates

Publication Date

20260512

Application Date

20220607

Claims (7)

1. 1. The method for generating the impedance test file is characterized by comprising the following steps of: The method comprises the steps of S1, calling an ERP file and a TGZ file from a database by Genesis software, wherein the ERP file comprises impedance information of a PCB, the TGZ file comprises layer information of the PCB, the Genesis software outputs an EMM file according to the ERP file and the TGZ file, when the PCB is a splice plate, the EMM file comprises a PNL file and a SET file, the PNL file comprises splice plate instructions, the SET file comprises splice plate information and PCS files corresponding to each splice plate, the PCS file comprises positions, sizes and layers of welding plate points in the PCB, when the PCB is a non-splice plate, the EMM file comprises the PNL file and the PCS file, the PNL file comprises splice plate instructions, and the PCS file comprises positions, sizes and layers of welding plate points in the PCB; s2, the Genesis software identifies a grounding point according to the TGZ file; S3, the Genesis software identifies a single-ended impedance line and a differential impedance line according to the ERP file, and calculates the lengths of the single-ended impedance line and the differential impedance line; S4, locating the grounding point and endpoint coordinates of the single-ended impedance line with the length within a preset range and the two endpoint coordinates of the differential impedance line with the length within the preset range; S5, decoding the CSV file into a DIF file for output, and selecting a counterpoint site by Genesis software according to the PNL file, integrating the EMM file and the CSV file according to the counterpoint site, decoding the EMM file and the CSV file into a PCB file and outputting the PCB file.
2. 2. The method for generating an impedance test file according to claim 1, wherein the impedance information includes a layer to which the impedance line belongs, a design line width of the impedance line, a design line distance of the impedance line, a reference layer, an impedance value, and an impedance tolerance.
3. 3. The method of claim 2, wherein in step S3, if the design line spacing of the impedance line is greater than 0, the impedance line is differential impedance, and if the impedance line has no design line spacing information, the impedance line is single-ended impedance.
4. 4. The method of claim 1, wherein the predetermined range in step S4 is greater than 2inch.
5. 5. The method of generating an impedance test file according to claim 4, wherein step S4 comprises: s41, aiming at a single-ended impedance line, automatically finding out a grounding wire within a range of 4mm of an endpoint in the single-ended impedance line by Genesis software, and preferentially outputting the grounding point and endpoint coordinates of the single-ended impedance line with the length of more than 6 inches; s42, outputting two end point coordinates of the differential impedance line with the length larger than 6 inches by Genesis software preferentially aiming at the differential impedance line, and outputting two end point coordinates of the single-ended impedance line with the length larger than 2 inches and smaller than 6 inches.
6. 6. An electronic device, comprising: Processor, and A memory having executable code stored thereon, which when executed by the processor, causes the processor to perform the method of any of claims 1-5.
7. 7. A non-transitory machine-readable storage medium having stored thereon executable code, which when executed by a processor of an electronic device, causes the processor to perform the method of any of claims 1-5.

Description

Impedance test file generation method Technical Field The invention relates to the field of impedance test files, in particular to a method for generating an impedance test file. Background Currently, the PCB impedance testing method is roughly divided into manual testing and automatic testing, wherein the manual testing efficiency is extremely low, and it is difficult to meet the increasing production requirements, and the automatic testing naturally becomes a trend. Before the automatic impedance test, a corresponding impedance test file must be manufactured, that is, the impedance requirement of the customer and the related information are output to the file in a fixed format, and then the automatic impedance test equipment determines whether the corresponding impedance value meets the requirement set by the customer according to the test file. Therefore, the manufacturing of the impedance test file is particularly important in automatic test, and the most original manufacturing method is to use manual operation, so that the efficiency is low and the accuracy is not guaranteed. The preparation of the early impedance test file can be completed through the combined output of various PCB aided design software (IGI, TDRSurpport, TPG, ERP, genesis) and the like, and because the used software is numerous and all the software needs manual operation, the steps are tedious and lengthy, so the learning difficulty is high and the training period is long, and as the integration degree of the PCB is more and more dense, the level of the PCB design is also higher and the number of impedance groups needing to be controlled is also more and more, and the manual operation is easy to cause the conditions of missing selection, wrong selection and wrong selection. Disclosure of Invention The present invention is directed to solving, at least to some extent, one of the problems in the related art. Therefore, the invention aims to provide a method for generating an impedance test file, which can automatically output a grounding point and an impedance line, can output all data at one time and ensures that the impedance test file can be generated quickly and effectively. In order to achieve the purpose, the application adopts the following technical scheme that the method for generating the impedance test file comprises the following steps: S1, calling an ERP file and a TGZ file from a database by Genesis software, wherein the ERP file comprises impedance information of a PCB, and the TGZ file comprises layer information of the PCB; S2, the Genesis software identifies a grounding point according to the TGZ file; S3, the Genesis software identifies a single-ended impedance line and a differential impedance line according to the ERP file, and calculates the lengths of the single-ended impedance line and the differential impedance line; S4, locating the grounding point and endpoint coordinates of the single-ended impedance line with the length within a preset range and the two endpoint coordinates of the differential impedance line with the length within the preset range; s5, decoding the CSV file into a DIF file for output. Further, the impedance information includes a layer to which the impedance line belongs, a design line width of the impedance line, a design line distance of the impedance line, a reference layer, an impedance value and an impedance tolerance. Further, in step S3, if the design line distance of the impedance line is greater than 0, the impedance line is differential impedance, and if the impedance line has no design line distance information, the impedance line is single-ended impedance. Further, the Genesis software outputs an EMM file according to the ERP file and the TGZ file, when the PCB board is a splice board, the EMM file includes a PNL file and a SET file, the PNL file includes a splice instruction, the SET file includes splice information and a PCS file corresponding to each splice, and the PCS file includes a position, a size and a layer of a solder pad point in the PCB board. Further, when the PCB board is a non-splice board, the EMM file includes a PNL file and a PCS file, where the PNL file includes a splice instruction, and the PCS file includes a position, a size, and a layer where a pad point in the PCB board is located. Further, genesis software selects an alignment point according to the PNL file, integrates and decodes the EMM file and the CSV file into a PCB file according to the alignment point, and outputs the PCB file. Further, in step S4, the preset range is greater than 2inch. Further, step S4 includes: S41, aiming at a single-ended impedance line, automatically finding out a grounding wire within a range of 4mm of an endpoint in the single-ended impedance line by Genesis software, and preferentially outputting the grounding point and endpoint coordinates of the single-ended impedance line with the length of more than 6 inches; S42, outputting two end point coordinates of the differen