CN-115188805-B - Heterojunction bipolar transistor

CN115188805BCN 115188805 BCN115188805 BCN 115188805BCN-115188805-B

Abstract

The present invention provides an HBT capable of inhibiting linearity reduction of input/output characteristics of the HBT. A collector layer, a base layer, and an emitter layer are stacked on the substrate. The collector layer comprises a graded semiconductor layer having an electron affinity that increases from a side closer to the base layer toward a side farther from the base layer. The electron affinity on the interface of the side of the base layer close to the collector layer is equal to the electron affinity on the interface of the side of the graded semiconductor layer close to the base layer.

Inventors

YASUNARI UMEMOTO
KOYA SHIGEKI
Da Bugong

Assignees

株式会社村田制作所

Dates

Publication Date: 20260505
Application Date: 20180926
Priority Date: 20171013

Claims (11)

1. A heterojunction bipolar transistor, wherein, Comprising a collector layer, a base layer and an emitter layer laminated on a substrate, The collector layer comprises a graded semiconductor layer, wherein electron affinity increases from a side proximal to the base layer towards a side distal to the base layer, The material of the base layer near the interface of the collector layer is the same as the material of the graded semiconductor layer near the interface of the base layer, The base layer is formed of AlGaAs, and The graded semiconductor layer is formed of AlGaAs, And an intermediate layer between the base layer and the graded semiconductor layer, Wherein the intermediate layer is formed of GaAs.
2. The heterojunction bipolar transistor of claim 1, wherein, The AlAs mixed crystal ratio of the base layer decreases from an interface near the emitter layer toward an interface near the collector layer.
3. The heterojunction bipolar transistor of claim 1, wherein, The electron affinity of the base layer increases from an interface proximate the emitter layer toward an interface proximate the collector layer.
4. The heterojunction bipolar transistor of claim 1, wherein, The base layer is formed of AlGaAs, and The AlAs mixed crystal ratio of the base layer decreases from an interface near the emitter layer toward an interface near the collector layer.
5. The heterojunction bipolar transistor of claim 1, wherein, The collector layer includes a first portion that is a portion proximate the base layer and a second portion that is a remaining portion distal from the base layer, an The doping concentration of the first portion is lower than the doping concentration of the second portion.
6. The heterojunction bipolar transistor of claim 5, wherein, The first portion is formed of at least one semiconductor selected from the group consisting of an n-type semiconductor having a doping concentration of 3×1015cm-3 or less, a p-type semiconductor having a doping concentration of 1×1015cm-3 or less, and an intrinsic semiconductor.
7. The heterojunction bipolar transistor of claim 5, wherein, The second portion includes a third portion that is a portion proximal to the first portion and a fourth portion that is a remaining portion distal from the first portion, an The doping concentration of the third portion is lower than the doping concentration of the fourth portion.
8. The heterojunction bipolar transistor of claim 7, further comprising: a sub-collector layer which is formed of an n-type semiconductor, is disposed on the substrate, and functions as a path for allowing a current to flow to the collector layer, The collector layer is disposed on the subcollector layer, an The doping concentration of the first portion and the third portion is 1/10 or less of the doping concentration of the subcollector layer.
9. The heterojunction bipolar transistor of claim 8, wherein, The doping concentration of the fourth portion is 0.5 to 1.5 times that of the subcollector layer.
10. The heterojunction bipolar transistor of claim 5, wherein, The second portion includes a third portion that is a portion proximal to the first portion and a fourth portion that is a remaining portion distal from the first portion, an The doping concentration of the third portion is lower than the doping concentration of the fourth portion.
11. The heterojunction bipolar transistor of claim 10, further comprising: a sub-collector layer which is formed of an n-type semiconductor, is disposed on the substrate, and functions as a path for allowing a current to flow to the collector layer, The collector layer is disposed on the subcollector layer, an The doping concentration of the first portion and the third portion is 1/10 or less of the doping concentration of the subcollector layer.

Description

Heterojunction bipolar transistor Technical Field The present invention relates to heterojunction bipolar transistors. Background As a transistor constituting a power amplifier module of a portable terminal, a Heterojunction Bipolar Transistor (HBT) is mainly used. Characteristics required for HBTs include high efficiency, high gain, high output, high withstand voltage, low distortion, and the like in a high frequency range. In particular, recently, HBTs operating at high output are required to have low distortion and high performance (high efficiency and high gain). Patent document 1 discloses an HBT for the purpose of achieving high efficiency. The HBT includes an emitter layer, a base layer, a collector layer, and a subcollector layer in this order. The collector layer comprises a plurality of adjacent sub-regions. In each sub-region, the bandgap is fixed or varies linearly. Between the sub-regions, the band edges of the charge carrier travel in the collector are continuous. A two-dimensional or pseudo-two-dimensional charge layer is formed at the interface between the sub-regions to compensate for the pseudo-electric field generated by the difference in electron affinity and band gap between the sub-regions. One sub-region of the collector layer is formed of a graded semiconductor having an electron affinity that increases gradually from the base layer toward the subcollector layer. Between the sub-region (graded semiconductor layer) and the base layer, a sub-region (graded semiconductor layer) composed of a graded semiconductor having an electron affinity gradually decreasing from the base layer toward the subcollector layer is arranged. At the interface between the graded semiconductor layer and the reverse graded semiconductor layer, a two-dimensional charge layer (delta-doped layer) is arranged. The graded semiconductor layer is a semiconductor layer in which the mixed crystal ratio of constituent elements of a mixed crystal semiconductor is changed so that electron affinity gradually increases from the base layer toward the sub-collector layer. And a semiconductor layer in which the mixed crystal ratio of constituent elements of the electron affinity mixed crystal semiconductor is changed so that the electron affinity gradually decreases from the base layer toward the subcollector layer. The HBT has a heterojunction formed by a collector layer and a base layer, and is classified as a so-called Double Heterojunction Bipolar Transistor (DHBT). In DHBT, it is expected to increase the efficiency of the power amplifier by reducing the bias voltage. In DHBT, it is expected to improve efficiency by reducing the bias voltage, but an obstacle called blocking effect occurs in electron transport due to an energy barrier formed at the interface between the reverse graded semiconductor layer and the graded semiconductor layer. The blocking effect may not effectively improve the efficiency of DHBT. In the DHBT disclosed in patent document 1, the efficiency is improved by disposing a delta doped layer at the interface between the reverse graded semiconductor layer and the graded semiconductor layer to reduce the energy barrier. Patent document 1 Japanese patent laid-open No. 2000-332023 As a result of the study by the inventors of the present application, it was found that in the DHBT structure disclosed in patent document 1, linearity of input/output characteristics at the time of high output is reduced (distortion is increased). The reason why the linearity of the input-output characteristic is lowered at the time of high output is as follows. In the HBT disclosed in patent document 1, a region of high concentration is present in the collector layer in the vicinity of the base layer by disposing the delta doping layer. This high concentration region is an important factor for reducing the linearity of the voltage dependence (Cbc-Vbc characteristic) of the base-collector capacitance. The decrease in linearity of Cbc-Vbc characteristics causes deterioration of adjacent channel leakage power ratio (ACLR), which is one index indicating distortion of the power amplifier. Disclosure of Invention The present invention aims to provide an HBT capable of inhibiting the linearity reduction of the input-output characteristics of the HBT. The heterojunction bipolar transistor of the first aspect of the present invention, Comprising a collector layer, a base layer and an emitter layer laminated on a substrate, The collector layer includes a graded semiconductor layer having electron affinity increasing from a side closer to the base layer toward a side farther from the base layer, The electron affinity at the interface of the base layer on the side close to the collector layer is equal to the electron affinity at the interface of the graded semiconductor layer on the side close to the base layer. An energy barrier for electrons is not formed at the interface between the base layer and the collector layer. No energy barrier f