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CN-115202612-B - Superconducting single-flux quantum clock domain crossing communication method and system based on asynchronous FIFO

CN115202612BCN 115202612 BCN115202612 BCN 115202612BCN-115202612-B

Abstract

The invention provides a superconducting single-flux quantum cross-clock domain communication method and system based on an asynchronous FIFO (first in first out), which comprises the steps of initializing the FIFO, inputting a write signal to the FIFO by an external write circuit, generating a write address and a write mark by the FIFO according to the write signal, comparing the write address with a read address and the read mark, waiting for the external read circuit to read data and generate a new read mark and a new read address if the read address is equal to the write address, and writing the data to be written into the FIFO according to the write address if the read address is not equal to the write address, otherwise writing the data to be written into the FIFO according to the write address. The external read circuit inputs a read signal to the FIFO, generates a read address and a read mark, compares the read address and the read mark with the write address and the write mark, and executes the process of waiting for the external write circuit to write data to generate a new write address and a new write mark if the read address and the write address are the same, and then reads the data according to the read address to return to the external read circuit, otherwise, reads the data according to the read address to return to the external read circuit.

Inventors

  • LIU JIAN
  • TANG GUANGMING
  • YANG JIAHONG
  • ZHENG XIANGYU

Assignees

  • 中国科学院计算技术研究所

Dates

Publication Date
20260505
Application Date
20220314

Claims (8)

  1. 1. An asynchronous FIFO-based superconducting single flux quantum clock domain crossing communication method is characterized by comprising the following steps: Initializing a FIFO (first in first out), inputting a write signal to the FIFO by an external write circuit, generating a write address and a write mark by the FIFO according to the write signal, comparing the write address with the read address and the read mark, and executing the step 2 if the read address is equal to the write address but the write mark is opposite to the read mark; step 2, after the FIFO is fully written at the moment and the external reading circuit reads out data and generates a new reading mark and a new reading address, writing the data to be written into the FIFO according to the writing address; step 3, the external reading circuit inputs a reading signal to the FIFO, generates a reading address and a reading mark, compares the reading address and the writing mark with the writing address and the writing mark, executes step 4 if the reading address and the writing address are the same and the reading mark and the writing mark are the same, otherwise, reads data according to the reading address and returns to the external reading circuit; step 4, when the FIFO is empty, after the external write circuit writes data to generate a new write address and a write mark, reading the data according to the read address and returning to the external read circuit; The FIFO comprises a register file, a read control circuit and a write control circuit; The write control circuit consists of an address generator, an address register, a data register, a full judging circuit and a clock gating circuit; The address generator consists of a plurality of D triggers, rtffl and a non-destructive readout unit, and is used for clearing all units in the address generator when a reset signal arrives, inputting a pulse to the D trigger at the lowest position, wherein the pulse is shifted upwards by one bit each time, the outputs of all the D triggers are also combined into a group of addresses when the clock arrives, wherein only the D trigger originally containing the pulse is output to be 1, the rest outputs are all 0, after the pulse arrives at the D trigger at the highest position, the clock again outputs a pulse to rtffl and the clearing end of the non-destructive readout unit, clears the non-destructive readout unit, and then if the pulse arrives at the odd number of the pulse of rtffl, rtffl outputs a pulse to the non-destructive readout unit, otherwise, when the pulse arrives in the non-destructive readout unit, each clock, the non-destructive readout unit outputs a pulse, and the output of the address generator is the address output by all the D triggers and the address output by the non-destructive readout unit; the address register consists of a plurality of D triggers, the input is the address output by the address generator, and the stored address is output after the clock arrives; The data register consists of a plurality of D flip-flops, inputs multi-bit data given externally, and outputs the multi-bit data after the clock arrives; The full judging circuit consists of an address comparing circuit, a mark comparing circuit and a full mark generating circuit; The address comparison circuit comprises a plurality of non-destructive reading units and a plurality of layers of fusion buffers, wherein the input of the non-destructive reading units is the read address of the read control circuit, the clock is the write address of the write control circuit, and the clearing signal is the read clock transmitted by the control circuit; when the read-write addresses are equal, the read control circuit firstly clears all the non-destructive read-out units in the address comparison circuit after generating the addresses, then the read addresses are sent to all the non-destructive read-out units in the address comparison circuit, the write address generator sends the addresses to the clock circuits of all the non-destructive read-out units in the address comparison circuit after outputting a group of addresses, when the read-write addresses are equal, one non-destructive read-out unit in the address comparison circuit has both data and clock, so a pulse is output, and the pulse is output after being subjected to the multi-layer fusion buffer; The mark comparison circuit consists of a non-destructive reading unit and an exclusive OR gate, wherein the input of the non-destructive reading unit is a read address mark of the read control circuit, the clock of the non-destructive reading unit is a write clock, the clearing circuit is a read clock, the input of the exclusive OR gate is the output of the write address mark and the non-destructive reading unit respectively, the clock is a write clock, the read control circuit sends the read mark to the non-destructive reading unit of the mark comparison circuit after generating one read mark, the non-destructive reading unit of the mark comparison circuit can be read after the write clock arrives, the clock of the exclusive OR gate reaches the exclusive OR gate after the input of the exclusive OR gate arrives, and the read address mark can generate output when the input of the exclusive OR gate is different; The data input of the full mark generating circuit is the output of the mark comparing circuit, the clock is the output of the address comparing circuit, the clearing circuit is the writing clock, the writing clock reaches the D trigger of the full mark generating circuit to clear the D trigger once, then the output of the mark comparing circuit arrives, then the output of the address comparing circuit arrives, and if the data and the clock arrive in one writing clock period, the output is generated; The clock gating circuit consists of a plurality of D triggers and a non-destructive reading unit, wherein the input of the non-destructive reading unit is a reset signal and a full mark signal passing through the two-stage D triggers, the clock is a write clock which is directly input, the clear signal is the full mark signal, the non-destructive reading unit of the clock gating circuit directly controls the clock, when the non-destructive reading unit has data, the clock can act on the D triggers which store the write signal after passing through the non-destructive reading unit, and when the non-destructive reading unit does not have data, the clock is shielded, and the write circuit stops working; the read control circuit consists of an address generating circuit, an address register, a judging circuit and a clock gating circuit; the composition and working principle of the address generating circuit, the address register and the clock gating circuit of the read control circuit are the same as those of the address generating circuit, the address register and the clock gating circuit of the write control circuit; The mark comparison circuit of the empty judging circuit is provided with one more NOT gate, the write address mark is inverted once before entering the non-destructive reading unit, the NOT gate clock is a write clock, and the rest circuits of the empty judging circuit are identical to the full judging circuit of the write control circuit.
  2. 2. The superconducting single flux quantum cross-clock domain communication method based on asynchronous FIFO as claimed in claim 1, The process of generating the write address and the write mark according to the write signal in the step 1 comprises resetting the write mark and the write address according to the initialization signal, wherein the write address is increased by one every time the FIFO receives the write signal, and the write mark is inverted and the write address is reset after the write address is increased for a designated number of times; the process of generating the read address and the read flag in the step 3 is specifically to reset the read flag and the read address according to the initialization signal, then the read address is increased by one every time the FIFO receives the read signal, and after the read address is increased by the designated times, the read flag is inverted and the read address is reset.
  3. 3. The method of claim 1, wherein the write address and the read address are each encoded unithermally.
  4. 4. An asynchronous FIFO-based superconducting single flux quantum clock domain crossing communication system, comprising: the writing module is used for initializing the FIFO, the external writing circuit inputs a writing signal to the FIFO, the FIFO generates a writing address and a writing mark according to the writing signal, and compares the writing address with the reading address and the reading mark, if the reading address is equal to the writing address, but the writing mark is opposite to the reading mark, the first waiting module is called, and otherwise, the data to be written is written into the FIFO according to the writing address; the first waiting module is used for waiting for an external reading circuit to read out data and generate a new reading mark and a new reading address, and writing the data to be written into the FIFO according to the writing address; The reading module is used for inputting a reading signal to the FIFO by the external reading circuit, generating a reading address and a reading mark, comparing the reading address with the writing address and the writing mark, calling a second waiting module if the reading address is the same as the writing address and the reading mark is the same as the writing address, and otherwise, reading data according to the reading address and returning the data to the external reading circuit; The second waiting module is used for waiting for the external read circuit to read data according to the read address after the external write circuit writes the data to generate a new write address and a write mark; The FIFO comprises a register file, a read control circuit and a write control circuit; The write control circuit consists of an address generator, an address register, a data register, a full judging circuit and a clock gating circuit; The address generator consists of a plurality of D triggers, rtffl and a non-destructive readout unit, and is used for clearing all units in the address generator when a reset signal arrives, inputting a pulse to the D trigger at the lowest position, wherein the pulse is shifted upwards by one bit each time, the outputs of all the D triggers are also combined into a group of addresses when the clock arrives, wherein only the D trigger originally containing the pulse is output to be 1, the rest outputs are all 0, after the pulse arrives at the D trigger at the highest position, the clock again outputs a pulse to rtffl and the clearing end of the non-destructive readout unit, clears the non-destructive readout unit, and then if the pulse arrives at the odd number of the pulse of rtffl, rtffl outputs a pulse to the non-destructive readout unit, otherwise, when the pulse arrives in the non-destructive readout unit, each clock, the non-destructive readout unit outputs a pulse, and the output of the address generator is the address output by all the D triggers and the address output by the non-destructive readout unit; the address register consists of a plurality of D triggers, the input is the address output by the address generator, and the stored address is output after the clock arrives; The data register consists of a plurality of D flip-flops, inputs multi-bit data given externally, and outputs the multi-bit data after the clock arrives; The full judging circuit consists of an address comparing circuit, a mark comparing circuit and a full mark generating circuit; The address comparison circuit comprises a plurality of non-destructive reading units and a plurality of layers of fusion buffers, wherein the input of the non-destructive reading units is the read address of the read control circuit, the clock is the write address of the write control circuit, and the clearing signal is the read clock transmitted by the control circuit; when the read-write addresses are equal, the read control circuit firstly clears all the non-destructive read-out units in the address comparison circuit after generating the addresses, then the read addresses are sent to all the non-destructive read-out units in the address comparison circuit, the write address generator sends the addresses to the clock circuits of all the non-destructive read-out units in the address comparison circuit after outputting a group of addresses, when the read-write addresses are equal, one non-destructive read-out unit in the address comparison circuit has both data and clock, so a pulse is output, and the pulse is output after being subjected to the multi-layer fusion buffer; The mark comparison circuit consists of a non-destructive reading unit and an exclusive OR gate, wherein the input of the non-destructive reading unit is a read address mark of the read control circuit, the clock of the non-destructive reading unit is a write clock, the clearing circuit is a read clock, the input of the exclusive OR gate is the output of the write address mark and the non-destructive reading unit respectively, the clock is a write clock, the read control circuit sends the read mark to the non-destructive reading unit of the mark comparison circuit after generating one read mark, the non-destructive reading unit of the mark comparison circuit can be read after the write clock arrives, the clock of the exclusive OR gate reaches the exclusive OR gate after the input of the exclusive OR gate arrives, and the read address mark can generate output when the input of the exclusive OR gate is different; The data input of the full mark generating circuit is the output of the mark comparing circuit, the clock is the output of the address comparing circuit, the clearing circuit is the writing clock, the writing clock reaches the D trigger of the full mark generating circuit to clear the D trigger once, then the output of the mark comparing circuit arrives, then the output of the address comparing circuit arrives, and if the data and the clock arrive in one writing clock period, the output is generated; The clock gating circuit consists of a plurality of D triggers and a non-destructive reading unit, wherein the input of the non-destructive reading unit is a reset signal and a full mark signal passing through the two-stage D triggers, the clock is a write clock which is directly input, the clear signal is the full mark signal, the non-destructive reading unit of the clock gating circuit directly controls the clock, when the non-destructive reading unit has data, the clock can act on the D triggers which store the write signal after passing through the non-destructive reading unit, and when the non-destructive reading unit does not have data, the clock is shielded, and the write circuit stops working; the read control circuit consists of an address generating circuit, an address register, a judging circuit and a clock gating circuit; the composition and working principle of the address generating circuit, the address register and the clock gating circuit of the read control circuit are the same as those of the address generating circuit, the address register and the clock gating circuit of the write control circuit; The mark comparison circuit of the empty judging circuit is provided with one more NOT gate, the write address mark is inverted once before entering the non-destructive reading unit, the NOT gate clock is a write clock, and the rest circuits of the empty judging circuit are identical to the full judging circuit of the write control circuit.
  5. 5. The superconducting single flux quantum cross-clock domain communication system based on asynchronous FIFO as claimed in claim 4, The write module is used for generating a write address and a write mark according to the write signal, and specifically, resetting the write mark and the write address according to an initialization signal, wherein the write address is increased by one when the FIFO receives the write signal once, and the write mark is inverted and the write address is reset after the write address is increased for a designated number of times; the read module is used for generating a read address and a read mark, and specifically comprises the steps of resetting the read mark and the read address according to an initialization signal, adding one read address each time the FIFO receives a read signal, inverting the read mark and resetting the read address after adding the read address for each designated times.
  6. 6. The superconducting single flux quantum cross-clock domain communication system of claim 5, wherein the write address and the read address are each encoded unithermally.
  7. 7. A storage medium storing a program for executing the superconducting single flux quantum cross-clock domain communication method based on an asynchronous FIFO as claimed in any one of claims 1 to 3.
  8. 8. A client for an asynchronous FIFO based superconducting single flux quantum clock domain communication system according to any one of claims 4 to 6.

Description

Superconducting single-flux quantum clock domain crossing communication method and system based on asynchronous FIFO Technical Field The present invention relates to the field of superconducting single flux quantum (RSFQ) microprocessors in computer systems, and in particular to clock domain crossing communication of superconducting single flux quantum processors. Background When asynchronous clock domain communication is performed, the clock frequencies and phases of different clock domains may be different, so that problems such as data loss, instability and the like are likely to occur when the cross-clock domain communication is performed. For these problems, one solution in the semiconductor field is to use an asynchronous FIFO, in which a circuit in the source clock domain writes data into the asynchronous FIFO in sequence, a circuit in the destination clock domain reads data out in sequence, and the asynchronous FIFO is used to store data, determine whether the data is full or not, whether the data is empty or not, and avoid data errors when an indefinite state occurs. The field of RSFQ circuits does not have asynchronous FIFOs which can be used for communication across clock domains at present, and due to the difference between a semiconductor circuit and an RSFQ circuit, the asynchronous FIFOs in the semiconductor circuit are directly realized by the RSFQ circuit, and the problems are that firstly, addresses are generated when the number of registers is small, the conversion into Hamming codes consumes too much resources when the circuits are decoded, and secondly, the semiconductor FIFO converts the addresses into the Hamming codes in order to reduce the probability of metastable states, so that only one address is changed when the addresses are generated each time, and the error probability is reduced, but due to the difference between the RSFQ circuit and the semiconductor circuit, the design is not used in the RSFQ circuit. That is, because the signals in the circuit change when the address changes, and the asynchronous FIFO needs to cross clock domains, the fewer the number of signals to be changed, the better, and the fewer the probability of generating an unstable state is easily reduced. In the semiconductor circuit, the level of two signal lines is turned over every time the address is changed by using the single thermal code, and only one signal line is turned over by using the Hamming code, and the address range which can be represented by the Hamming code is larger by using the same number of signal lines, so that the semiconductor adopts the Hamming code. Whereas the signal in rsfq circuits is not a level signal but a pulse signal. The 1 and 0 are indicated by the presence or absence of a pulse between the two clocks, with a pulse 1 between the two clocks and a no pulse 0. Therefore, in the clock domain crossing communication, rsfq circuits pursue a small number of pulses, and the smaller the number of pulses, the less prone to error, so onehot codes with only one 1 are adopted. Therefore, the asynchronous FIFO in the semiconductor field cannot be directly applied to the RSFQ field. There is therefore a need for an asynchronous FIFO that can be used in the RSFQ circuit environment to match the clock frequency and phase of different clock domains. Disclosure of Invention The invention aims to solve the problem of clock domain crossing communication of an RSFQ circuit and provides an asynchronous FIFO applicable to the RSFQ circuit. Aiming at the defects of the prior art, the invention provides a superconducting single-flux quantum clock domain crossing communication method based on asynchronous FIFO, which comprises the following steps: Initializing a FIFO (first in first out), inputting a write signal to the FIFO by an external write circuit, generating a write address and a write mark by the FIFO according to the write signal, comparing the write address with the read address and the read mark, and executing the step 2 if the read address is equal to the write address but the write mark is opposite to the read mark; step 2, after the FIFO is fully written at the moment and the external reading circuit reads out data and generates a new reading mark and a new reading address, writing the data to be written into the FIFO according to the writing address; step 3, the external reading circuit inputs a reading signal to the FIFO, generates a reading address and a reading mark, compares the reading address and the writing mark with the writing address and the writing mark, executes step 4 if the reading address and the writing address are the same and the reading mark and the writing mark are the same, otherwise, reads data according to the reading address and returns to the external reading circuit; and 4, when the FIFO is empty, waiting for the external write circuit to write data to generate a new write address and a write mark, and reading the data according to the read address and retu