CN-115208391-B - Clock signal measuring circuit, clock signal processing device and chip

Abstract

The embodiment of the application discloses a clock signal measuring circuit, a clock signal processing device and a chip, wherein the clock signal measuring circuit comprises a first counting unit, a counting control unit and a second counting unit, the first counting unit is used for starting counting a preset clock signal according to an updating signal to obtain and output a first period number, the counting control unit is used for sending a starting instruction to a control end of the second counting unit when the first counting unit starts counting the preset clock signal and sending a stopping instruction to the control end of the second counting unit when the first period number reaches a preset value, and the second counting unit is used for starting counting the clock signal to be measured in response to the starting instruction and stopping counting the clock signal to be measured in response to the stopping instruction to obtain and output a final value of a second period number. The application can realize accurate measurement of the high-speed on-chip clock frequency.

Inventors

• ZHANG QIFU

Assignees

• 芯盟科技有限公司

Dates

Publication Date

20260508

Application Date

20220721

Claims (11)

1. 1. The clock signal measuring circuit is characterized by comprising a first counting unit, a counting control unit and a second counting unit; The input end of the first counting unit receives a preset clock signal, the control end of the first counting unit receives an update signal and is used for starting to count the preset clock signal according to the update signal to obtain and output a first period number; The input end of the counting control unit receives the first period number, and is used for sending a starting instruction to the control end of the second counting unit when the first period number is accumulated to be 1, and sending a stopping instruction to the control end of the second counting unit when the first period number reaches a preset value; The input end of the second counting unit receives a clock signal to be measured, and is used for starting to count the clock signal to be measured in response to the starting instruction, stopping to count the clock signal to be measured in response to the stopping instruction, and obtaining and outputting a final value of a second cycle number; The clock signal measuring circuit is used for calculating the frequency of the clock signal to be measured according to the value obtained by subtracting 1 from the preset value of the first period number, the final value of the second period number and the period of the preset clock signal.
2. 2. The clock signal measurement circuit of claim 1, further comprising a first register unit; The input end of the first register unit is electrically connected to the output end of the second counting unit, and the first register unit is used for registering the final value of the second cycle number and outputting the final value of the second cycle number through the first output end of the first register unit.
3. 3. The clock signal measurement circuit of claim 2, further comprising a first control gate; The first input end of the first control gate receives the preset clock signal, and the output end of the first control gate is electrically connected with the input end of the first counting unit; The first register unit is further used for outputting a first monitoring enabling signal to the second input end of the first control gate through the second output end of the first register unit so as to control the preset clock signal to be transmitted to the first counting unit.
4. 4. The clock signal measurement circuit of claim 3, further comprising a second control gate; The first input end of the second control gate receives the clock signal to be detected, and the output end of the second control gate is electrically connected with the input end of the second counting unit; the first register unit is further used for outputting the first monitoring enabling signal to the second input end of the second control gate through the second output end of the first register unit so as to control the clock signal to be tested to be transmitted to the second counting unit.
5. 5. The clock signal measurement circuit of claim 2, further comprising a second register unit; The input end of the second register unit is electrically connected to the output end of the second counting unit, and the second register unit is used for registering and outputting the final value of the second cycle number.
6. 6. The clock signal measurement circuit of claim 5, wherein the final value of the second number of cycles comprises m bits of data, and the second register unit comprises m registers; the data input ends of the m registers are in one-to-one correspondence to receive the m-bit data, and the clock input ends of the m registers are all used for receiving the preset clock signals; the output end of each register is electrically connected with the scanning input end of the next register, and the output end of the mth register outputs the final value of the second period number.
7. 7. The clock signal measurement circuit of claim 6, further comprising m third control gates; The first input ends of the m third control gates are in one-to-one correspondence to receive the m-bit data, and the output ends of the m third control gates are in one-to-one correspondence to be electrically connected with the data input ends of the m registers; The first register unit is further configured to output a second monitor enable signal to the second input ends of the m third control gates through the third output ends thereof, so as to control the final value of the second cycle number to be transmitted to the second register unit.
8. 8. A clock signal processing apparatus is characterized by comprising a frequency calculation unit; The frequency calculating unit is configured to pre-store a frequency of a preset clock signal and a preset value of a corresponding first period number, receive a final value of a second period number corresponding to the clock signal to be measured, and calculate the frequency of the clock signal to be measured according to the frequency of the preset clock signal, a value obtained by subtracting 1 from the preset value of the first period number, and the final value of the second period number.
9. 9. The clock signal processing apparatus according to claim 8, further comprising a determination unit; The judging unit is used for receiving the final value of the second cycle number and judging whether the final value of the second cycle number meets a first judging condition or not, wherein the first judging condition is set based on the expected value of the frequency of the clock signal to be tested.
10. 10. The clock signal processing apparatus according to claim 9, further comprising a screening unit; The screening unit is configured to receive a final value of at least one second cycle number corresponding to at least one chip to be tested, determine the final value of at least one second cycle number according to a second determination condition, so as to screen out a compliant chip from at least one chip to be tested, where the second determination condition is set based on the first determination condition.
11. 11. A chip comprising the clock signal measurement circuit of any one of claims 1 to 7.

Description

Clock signal measuring circuit, clock signal processing device and chip Technical Field The present application relates to the field of integrated circuits, and more particularly, to a clock signal measurement circuit, a clock signal processing device, and a chip. Background In integrated circuits, high-Speed On-Chip Clock (High-Speed On-Chip Clock) is generated by a PLL (delay locked loop) to perform At-Speed testing of digital logic sequential circuits. In the related art, a method for measuring the frequency of a high-speed on-chip clock is lacking. Disclosure of Invention In view of the above, the embodiments of the present application provide a clock signal measurement circuit, a clock signal processing device and a chip, which can realize accurate measurement of high-speed on-chip clock frequency. The technical scheme of the embodiment of the application is realized as follows: the embodiment of the application provides a clock signal measuring circuit, which comprises a first counting unit, a counting control unit and a second counting unit; The input end of the first counting unit receives a preset clock signal, the control end of the first counting unit receives an update signal and is used for starting to count the preset clock signal according to the update signal to obtain and output a first period number; The input end of the counting control unit receives the first period number and is used for sending a starting instruction to the control end of the second counting unit when the first counting unit starts counting the preset clock signal, and sending a stopping instruction to the control end of the second counting unit when the first period number reaches a preset value; and the input end of the second counting unit receives a clock signal to be measured, and is used for starting to count the clock signal to be measured in response to the starting instruction, stopping to count the clock signal to be measured in response to the stopping instruction, and obtaining and outputting a final value of a second cycle number. In the scheme, the clock signal measuring circuit further comprises a first register unit, wherein the input end of the first register unit is electrically connected to the output end of the second counting unit, and the first register unit is used for registering the final value of the second cycle number and outputting the final value of the second cycle number through the first output end of the first register unit. In the scheme, the clock signal measuring circuit further comprises a first control gate, wherein a first input end of the first control gate receives the preset clock signal, an output end of the first control gate is electrically connected with an input end of the first counting unit, a second output end of the first register unit is electrically connected with a second input end of the first control gate, and the first register unit is further used for outputting a first monitoring enabling signal to the second input end of the first control gate through the second output end of the first register unit so as to control the preset clock signal to be transmitted to the first counting unit. In the scheme, the clock signal measuring circuit further comprises a second control gate, wherein the first input end of the second control gate receives the clock signal to be measured, the output end of the second control gate is electrically connected with the input end of the second counting unit, the second output end of the first register unit is further electrically connected with the second input end of the second control gate, and the first register unit is further used for outputting the first monitoring enabling signal to the second input end of the second control gate through the second output end of the first register unit so as to control the clock signal to be measured to be transmitted to the second counting unit. In the scheme, the clock signal measuring circuit further comprises a second register unit, wherein the input end of the second register unit is electrically connected to the output end of the second counting unit, and the second register unit is used for registering and outputting the final value of the second cycle number. In the above scheme, the final value of the second cycle number includes m-bit data, the second register unit includes m registers, the data input ends of the m registers receive the m-bit data in a one-to-one correspondence manner, the clock input ends of the m registers receive the preset clock signal, the output end of each register is electrically connected with the scan input end of the next register, and the output end of the m-th register outputs the final value of the second cycle number. In the scheme, the clock signal measuring circuit further comprises m third control gates, first input ends of the m third control gates are correspondingly used for receiving the m-bit data one by one, output ends of the m third control g