CN-115225085-B - Analog-digital converter device and correction circuit control method

Abstract

An analog-digital converter device and a correction circuit control method are provided, wherein the device comprises a plurality of analog-digital conversion circuits, a correction circuit and a control circuit. The analog-to-digital conversion circuits are used for generating a plurality of first quantized outputs according to a plurality of clock signals. The correction circuit is used for executing at least one error operation according to the first quantized outputs to generate a plurality of second quantized outputs, and analyzing a plurality of time difference information of a plurality of clock signals according to the second quantized outputs to generate a plurality of adjustment signals. The control circuit is used for analyzing a plurality of first quantized outputs to generate at least one control signal to the correction circuit, wherein the at least one control signal is used for controlling the correction circuit to selectively execute at least one error operation and selectively analyze a plurality of time difference information of a plurality of clock signals. The present disclosure generates at least one control signal for controlling the correction circuit through the control circuit, so as to avoid the problem that the correction performed by the correction circuit is affected by weak input signals.

Inventors

• Han Xinhan
• CHEN YUZHU
• KANG WENZHU

Assignees

• 创意电子股份有限公司
• 台湾积体电路制造股份有限公司

Dates

Publication Date

20260512

Application Date

20210421

Claims (20)

1. 1. An analog-to-digital converter apparatus, comprising: The analog-digital conversion circuits are used for converting an input signal according to a plurality of staggered clock signals so as to generate a plurality of first quantized outputs; A correction circuit for performing at least one error operation according to the first quantized outputs to generate at least one correction information, correcting the first quantized outputs with the at least one correction information to generate second quantized outputs, and analyzing time difference information of the clock signals according to the second quantized outputs to generate a plurality of adjustment signals to the analog-to-digital conversion circuits, wherein the adjustment signals are used for reducing clock skew of the analog-to-digital conversion circuits The control circuit is used for receiving the first quantized outputs and analyzing the first quantized outputs to generate at least one control signal to the correction circuit, wherein the at least one control signal is used for controlling the correction circuit to selectively execute the at least one error operation and selectively analyze the time difference information of the clock signals.
2. 2. The analog-to-digital converter apparatus of claim 1, wherein said control circuit analyzes said first quantized outputs of an nth period to generate said at least one control signal of an nth period, The correction circuit selectively performs the at least one error operation on the first quantized outputs of the n+1th period according to the at least one control signal of the n+1th period, and selectively analyzes the time difference information of the clock signals of the n+1th period, wherein N is a positive integer.
3. 3. The adc device according to claim 2, wherein when the correction circuit performs the at least one error operation on the plurality of first quantized outputs of the n+1 th period, the correction circuit corrects the plurality of first quantized outputs of the n+1 th period using the at least one correction information generated according to the plurality of first quantized outputs of the n+1 th period to generate the plurality of second quantized outputs of the n+1 th period.
4. 4. The analog-to-digital converter apparatus of claim 3, wherein when the correction circuit does not perform the at least one error operation on the plurality of first quantized outputs of the n+1 th period, the correction circuit corrects the plurality of first quantized outputs of the n+1 th period using the at least one correction information previously generated to generate the plurality of second quantized outputs of the n+1 th period.
5. 5. The adc device of claim 2, wherein the correction circuit analyzes the second quantized outputs of the n+1th period to generate the adjustment signals of the n+1th period when the correction circuit analyzes the time difference information of the clock signals of the n+1th period.
6. 6. The analog-to-digital converter apparatus according to claim 5, wherein the correction circuit outputs the plurality of adjustment signals of the N-th period when the correction circuit does not analyze the plurality of time difference information of the plurality of clock signals of the n+1-th period.
7. 7. The analog-to-digital converter apparatus of claim 1, wherein the control circuit comprises: A plurality of absolute value circuits for receiving the plurality of first quantized outputs to output a plurality of absolute value signals, wherein each absolute value circuit is used for performing an absolute value operation according to a corresponding first quantized output of the plurality of first quantized outputs to generate a corresponding absolute value signal of the plurality of absolute value signals; an averaging circuit for performing an averaging operation to average the absolute value signals to generate an average signal; A filter circuit for filtering the average signal, and And a comparison circuit for comparing the filtered average signal with at least one threshold value to generate the at least one control signal.
8. 8. The analog-to-digital converter apparatus of claim 1, wherein the correction circuit comprises: And a skew adjusting circuit for analyzing the second quantized outputs to generate the adjusting signals to the analog-to-digital converting circuits.
9. 9. The analog-to-digital converter apparatus of claim 1, wherein the at least one correction information comprises a gain correction information, the at least one error operation comprises a gain error operation, the correction circuit further comprising: and a gain correction circuit for performing the gain error operation according to the first quantized outputs to generate the gain correction information, and generating the second quantized outputs using the gain correction information.
10. 10. The analog-to-digital converter apparatus of claim 9, wherein the at least one correction information further comprises an offset correction information, the at least one error operation further comprises an offset error operation, the correction circuit further comprising: An offset correction circuit receives the plurality of first quantized outputs, performs the offset error operation according to the plurality of first quantized outputs to generate the offset correction information, and corrects the plurality of first quantized outputs by using the offset correction information to generate a plurality of third quantized outputs, wherein the gain correction circuit corrects the plurality of third quantized outputs by using the gain correction information to generate the plurality of second quantized outputs.
11. 11. A correction circuit control method, comprising: receiving a plurality of first quantized outputs generated by a plurality of analog-to-digital conversion circuits according to a plurality of interleaved clock signals through a control circuit; Analyzing the plurality of first quantized outputs by the control circuit to generate at least one control signal to a correction circuit; selectively performing at least one error operation according to the at least one control signal to generate at least one correction information, and selectively analyzing a plurality of time difference information of the plurality of clock signals to generate a plurality of adjustment signals to the plurality of analog-to-digital conversion circuits, wherein the plurality of adjustment signals are used for reducing clock skew of the plurality of analog-to-digital conversion circuits, and The plurality of first quantized outputs are corrected by the correction circuit to produce a plurality of second quantized outputs.
12. 12. The method of claim 11, wherein the control circuit analyzes the first quantized outputs of the nth period to generate the at least one control signal of the nth period, The correction circuit selectively performs the at least one error operation on the first quantized outputs of the n+1th period according to the at least one control signal of the n+1th period, and selectively analyzes the time difference information of the clock signals of the n+1th period, wherein N is a positive integer.
13. 13. The method according to claim 12, wherein when the correction circuit performs the at least one error operation on the plurality of first quantized outputs of the n+1 th period, the correction circuit corrects the plurality of first quantized outputs of the n+1 th period using the at least one correction information generated according to the plurality of first quantized outputs of the n+1 th period to generate the plurality of second quantized outputs of the n+1 th period.
14. 14. The method according to claim 13, wherein when the correction circuit does not perform the at least one error operation on the plurality of first quantized outputs of the n+1 th period, the correction circuit corrects the plurality of first quantized outputs of the n+1 th period using the at least one correction information generated previously to generate the plurality of second quantized outputs of the n+1 th period.
15. 15. The method according to claim 12, wherein when the correction circuit analyzes the time difference information of the clock signals of the n+1th period, the correction circuit analyzes the second quantized outputs of the n+1th period to generate the adjustment signals of the n+1th period.
16. 16. The correction circuit control method according to claim 15, wherein the correction circuit outputs the plurality of adjustment signals of the N-th period when the correction circuit does not analyze the plurality of time difference information of the plurality of clock signals of the n+1-th period.
17. 17. The method of claim 11, wherein generating the at least one control signal comprises: performing an absolute value operation according to a corresponding one of the first quantized outputs to generate a corresponding one of a plurality of absolute value signals; Performing an averaging operation to average the absolute value signals to generate an average signal; filtering the average signal, and Comparing the filtered average signal with at least one threshold value to generate the at least one control signal.
18. 18. The correction circuit control method of claim 11, wherein generating the plurality of adjustment signals comprises: Analyzing the second quantized outputs by a skew adjusting circuit of the correcting circuit to generate the adjusting signals to the analog-digital converting circuits.
19. 19. The method of claim 11, wherein the at least one correction message comprises a gain correction message, the at least one error operation comprises a gain error operation, and generating the plurality of second quantized outputs comprises: The gain correction information is generated by a gain correction circuit of the correction circuit according to the first quantized outputs, and the second quantized outputs are generated by using the gain correction information.
20. 20. The method of claim 19, wherein the at least one correction message further comprises an offset correction message, the at least one error operation further comprises an offset error operation, and the generating the plurality of second quantized outputs further comprises: receiving the plurality of first quantized outputs through an offset correction circuit of the correction circuit, and The offset correction circuit performs the offset error operation according to the first quantized outputs to generate offset correction information, and corrects the first quantized outputs to generate third quantized outputs by using the offset correction information, wherein the gain correction circuit corrects the third quantized outputs to generate the second quantized outputs by using the gain correction information.

Description

Analog-digital converter device and correction circuit control method Technical Field The present disclosure relates to an adc device and a correction circuit control method, and more particularly, to a time-interleaved adc device and a correction circuit control method. Background Analog-to-digital converter (ADC) is commonly used in various electronic devices for converting analog signals to digital signals for signal processing. In practical applications, the ADC may affect its resolution or linearity due to gain errors, offset errors, or timing errors. When the input signal is weak (for example, the amplitude is too small or the power is too small), the correction of the three errors in the prior art is easily affected, so that the phase errors between different channels may be incorrectly converged. Disclosure of Invention One aspect of the present disclosure is an analog-to-digital converter device. The analog-digital converter device comprises a plurality of analog-digital conversion circuits, a correction circuit and a control circuit. The analog-to-digital conversion circuits are used for converting an input signal according to a plurality of staggered clock signals so as to generate a plurality of first quantized outputs. The correction circuit is used for executing at least one error operation according to the first quantized outputs to generate at least one correction information, correcting the first quantized outputs by the at least one correction information to generate a plurality of second quantized outputs, and analyzing a plurality of time difference information of the clock signals according to the second quantized outputs to generate a plurality of adjustment signals, wherein the adjustment signals are used for reducing clock skew of the analog-digital conversion circuits. The control circuit receives the first quantized outputs and is used for analyzing the first quantized outputs to generate at least one control signal to the correction circuit, wherein the at least one control signal is used for controlling the correction circuit to selectively execute the at least one error operation and selectively analyze the time difference information of the clock signals. In another embodiment, the control circuit analyzes the first quantized outputs of the nth cycle to generate the at least one control signal of the nth cycle, the correction circuit selectively performs the at least one error operation on the first quantized outputs of the n+1th cycle according to the at least one control signal of the nth cycle, and selectively analyzes the time difference information of the clock signals of the n+1th cycle, wherein N is a positive integer. In another embodiment, when the correction circuit performs the at least one error operation on the first quantized outputs of the n+1th period, the correction circuit corrects the first quantized outputs of the n+1th period by using the at least one correction information generated according to the first quantized outputs of the n+1th period to generate the second quantized outputs of the n+1th period. In another embodiment, when the correction circuit does not perform the at least one error operation on the first quantized outputs of the n+1th cycle, the correction circuit corrects the first quantized outputs of the n+1th cycle by using the at least one correction information generated previously to generate the second quantized outputs of the n+1th cycle. In another embodiment, when the correction circuit analyzes the time difference information of the clock signals of the n+1th period, the correction circuit analyzes the second quantization outputs of the n+1th period to generate the adjustment signals of the n+1th period. In another embodiment, when the correction circuit does not analyze the time difference information of the clock signals in the n+1th period, the correction circuit outputs the adjustment signals in the N-th period. In another embodiment, the control circuit comprises a plurality of absolute value circuits for receiving the first quantized outputs to output a plurality of absolute value signals, wherein each absolute value circuit is used for executing an absolute value operation according to a corresponding first quantized output in the first quantized outputs to generate a corresponding absolute value signal in the absolute value signals, an average circuit for executing an average operation to average the absolute value signals to generate an average signal, a filter circuit for performing a filtering operation on the average signal, and a comparison circuit for comparing the filtered average signal with at least one critical value to generate the at least one control signal. In another embodiment, the correction circuit includes a skew adjustment circuit for analyzing the second quantized outputs to generate the adjustment signals to the analog-to-digital conversion circuits. In another embodiment, the at least one correction inf