CN-115240736-B - Data reading circuit of resistance random access memory and resistance random access memory circuit

CN115240736BCN 115240736 BCN115240736 BCN 115240736BCN-115240736-B

Abstract

The application discloses a data reading circuit and a resistance change memory circuit of a resistance change memory, wherein the data reading circuit of the resistance change memory comprises an adaptive sensitive current amplifier and a reference current generator, the adaptive sensitive current amplifier is used for being electrically connected with the resistance change memory, the adaptive sensitive current amplifier is electrically connected with the reference current generator, the reference current generator is used for generating basic reference current, the adaptive sensitive current amplifier is used for obtaining reference current according to the basic reference current and bit line current of the resistance change memory, and the adaptive sensitive current amplifier is used for comparing the reference current with the bit line current so as to read memory data. The problem of data read errors caused by high resistance state degradation of the resistance random access memory can be solved.

Inventors

ZHANG FENG
REN QIRUI

Assignees

中国科学院微电子研究所
中国科学院微电子研究所

Dates

Publication Date: 20260421
Application Date: 20210423
Priority Date: 20210423

Claims (8)

1. The data reading circuit of the resistive random access memory is characterized by comprising an adaptive sensitive current amplifier and a reference current generator, wherein the adaptive sensitive current amplifier is used for being electrically connected with the resistive random access memory, and is electrically connected with the reference current generator; the reference current generator is used for generating a basic reference current; The self-adaptive sensitive current amplifier is used for obtaining a reference current according to the basic reference current and the bit line current of the resistive random access memory; the adaptive sense current amplifier is used for comparing the reference current with the bit line current so as to read out storage data; the self-adaptive sensitive current amplifier comprises a data reading module and a reference current module; The data reading module is electrically connected with the reference current module, the data reading module is used for being electrically connected with the resistance random access memory, and the reference current module is respectively electrically connected with the resistance random access memory and the reference current generator; the reference current module is used for obtaining the reference current according to the basic reference current and the bit line current; the data reading module is used for comparing the reference current with the bit line current so as to read the stored data; the reference current module comprises a feedback unit and a plurality of amplifying units; The feedback unit is respectively and electrically connected with the resistance change memory and the amplifying unit, and the amplifying unit is respectively and electrically connected with the data reading module and the reference current generator; The feedback unit is used for generating an excitation response according to the bit line current of the resistance random access memory and controlling the conduction of the corresponding amplifying unit according to the excitation response; the amplifying unit is used for amplifying the basic reference current to obtain the corresponding reference current.
2. The data read-out circuit of a resistive random access memory according to claim 1, wherein a plurality of the amplifying units are connected in parallel, each of the amplifying units corresponding to an amplifying coefficient.
3. The data readout circuit of the resistive random access memory according to claim 2, wherein the amplifying unit includes a first MOS transistor, and a gate of the first MOS transistor is electrically connected to the feedback unit.
4. The data readout circuit of the resistive random access memory according to claim 2, wherein the amplifying unit comprises a second MOS transistor, and a third MOS transistor is arranged between the second MOS transistor and the reference current generator; And the channel width-to-length ratio of the third MOS tube multiplied by the amplification factor is equal to the channel width-to-length ratio of the corresponding second MOS tube.
5. The data readout circuit of a resistive random access memory according to claim 1, wherein the adaptive sense current amplifier comprises a pre-protection module; the data reading module comprises a bit line current input end, a reference current input end and a data reading end; The bit line current input end and the reference current input end are respectively and electrically connected with the front-end protection module.
6. The data read-out circuit of a resistive random access memory according to claim 1, wherein the reference current generator comprises a replica resistive random access memory module and a current generation module; The current generation module is used for generating the basic reference current when the replication resistance change memory module is in a low resistance state, wherein the current when the replication resistance change memory module is in the low resistance state is a low resistance current, and the low resistance current is twice the basic reference current.
7. The data read circuit of a resistive random access memory of claim 6, wherein the replica resistive memory module comprises a plurality of resistive memory cells.
8. A resistance random access memory circuit, comprising a resistance random access memory and a data readout circuit of the resistance random access memory according to any one of claims 1 to 6; the resistive random access memory comprises a resistive random access memory array and a data writing control circuit, wherein the resistive random access memory array is electrically connected with the data writing control circuit; the resistance change memory array is electrically connected with a data reading circuit of the resistance change memory; the resistive memory array includes a plurality of resistive memory cells.

Description

Data reading circuit of resistance random access memory and resistance random access memory circuit Technical Field The application relates to the technical field of circuits, in particular to a data reading circuit of a resistance random access memory and a resistance random access memory circuit. Background In recent years, resistive random access memory (RRAM, RESISTIVE RANDOM ACCESS MEMORY) has become an embedded nonvolatile memory under advanced technology nodes with good scalability, low power consumption and good compatibility with logic technology, and is widely applied to the fields of consumer electronics, automatic driving automobiles, industrial control, internet of things edge equipment and the like. However, with the use of the resistive random access memory, the resistive state of the resistive random access memory gradually degrades, that is, the resistance value of the high resistive state is greatly reduced or the resistance value of the low resistive state is greatly increased, which easily causes that the data reading circuit is difficult to normally distinguish the high resistive state and the low resistive state, and causes data reading errors. Disclosure of Invention The embodiment of the application provides a data reading circuit and a resistance change memory circuit of a resistance change memory, which can solve the problem of data reading errors caused by high resistance state degradation of the resistance change memory. The data reading circuit of the resistive random access memory comprises an adaptive sense current amplifier and a reference current generator, wherein the adaptive sense current amplifier is used for being electrically connected with the resistive random access memory and is electrically connected with the reference current generator; the reference current generator is used for generating a basic reference current; The self-adaptive sensitive current amplifier is used for obtaining a reference current according to the basic reference current and the bit line current of the resistive random access memory; The adaptive sense current amplifier is used for comparing the reference current with the bit line current to read out stored data. In one possible embodiment, the adaptive sense current amplifier includes a data sense module and a reference current module; The data reading module is electrically connected with the reference current module, the data reading module is used for being electrically connected with the resistance random access memory, and the reference current module is respectively electrically connected with the resistance random access memory and the reference current generator; the reference current module is used for obtaining the reference current according to the basic reference current and the bit line current; the data reading module is used for comparing the reference current with the bit line current so as to read the storage data. In a possible embodiment, the reference current module includes a feedback unit and a plurality of amplifying units; The feedback unit is respectively and electrically connected with the resistance change memory and the amplifying unit, and the amplifying unit is respectively and electrically connected with the data reading module and the reference current generator; The feedback unit is used for generating an excitation response according to the bit line current of the resistance random access memory and controlling the conduction of the corresponding amplifying unit according to the excitation response; the amplifying unit is used for amplifying the basic reference current to obtain the corresponding reference current. In a possible embodiment, a plurality of amplifying units are connected in parallel, and each amplifying unit corresponds to one amplifying coefficient. In one possible implementation manner, the amplifying unit includes a first MOS transistor, and a gate of the first MOS transistor is electrically connected to the feedback unit. In a possible implementation manner, the amplifying unit includes a second MOS transistor, and a third MOS transistor is disposed between the second MOS transistor and the reference current generator; And the channel width-to-length ratio of the third MOS tube multiplied by the amplification factor is equal to the channel width-to-length ratio of the corresponding second MOS tube. In one possible embodiment, the adaptive sense current amplifier includes a pre-protection module; the data reading module comprises a bit line current input end, a reference current input end and a data reading end; The bit line current input end and the reference current input end are respectively and electrically connected with the front-end protection module. In one possible embodiment, the reference current generator includes a replica resistance change memory module and a current generation module; The current generation module is used for generating the basic reference current when the r