CN-115242244-B - Control device, system and method of phase-locked loop

CN115242244BCN 115242244 BCN115242244 BCN 115242244BCN-115242244-B

Abstract

The application discloses a control device, a system and a method of a phase-locked loop, and belongs to the technical field of communication. The phase-locked loop control device comprises a collector, a memory and a controller which are sequentially connected. The collector is configured to collect characteristic data at an operating frequency at which the phase-locked loop is currently in operation, prior to an interruption of operation of the phase-locked loop. The memory is configured to store the characteristic data at the operating frequency. The controller is configured to read the characteristic data stored in the memory at the operating frequency after the current operation of the phase-locked loop is interrupted, and if the phase-locked loop needs to re-lock the operating frequency, control the phase-locked loop to re-lock the operating frequency based on the characteristic data at the operating frequency. The application collects and stores the characteristic data of the phase-locked loop under the locked working frequency, so that the phase-locked loop can be controlled to quickly relock the working frequency based on the characteristic data, thereby realizing the quick relock of the phase-locked loop.

Inventors

YUAN HAOYU
LI KUILI

Assignees

北京奕斯伟计算技术股份有限公司
北京奕斯伟计算技术股份有限公司

Dates

Publication Date: 20260421
Application Date: 20220628
Priority Date: 20220628

Claims (10)

1. A control device (10) of a phase-locked loop, wherein the control device (10) comprises a collector (11), a memory (12) and a controller (13), the input end of the collector (11) is connected with the phase-locked loop (20), the output end of the collector (11) is connected with the input end of the memory (12), the output end of the memory (12) is connected with the input end of the controller (13), and the output end of the controller (13) is connected with the phase-locked loop (20); The memory (12) is configured to store a first working frequency locked before the phase-locked loop (20) works this time and characteristic data at the first working frequency correspondingly; The collector (11) is configured to acquire the stored first working frequency before the current working of the phase-locked loop (20) is interrupted, compare the first working frequency with a second working frequency locked by the current working of the phase-locked loop (20), and collect characteristic data under the second working frequency if the second working frequency is different from the first working frequency; -the memory (12) is further configured to store the second operating frequency in correspondence with characteristic data at the second operating frequency; The controller (13) is configured to, after the current operation of the phase-locked loop (20) is interrupted, if the phase-locked loop (20) needs to relock the second operating frequency, query the second operating frequency from the stored first operating frequency and the second operating frequency, read the characteristic data stored in the memory (12) corresponding to the second operating frequency at the second operating frequency, and control the phase-locked loop (20) to relock the second operating frequency based on the characteristic data at the second operating frequency.
2. The control device (10) according to claim 1, characterized in that the controller (13) comprises an analog-to-digital, AD, to digital, DA, converter (14) and a comparator (15); The output end of the collector (11) is connected with the analog input end of the AD/DA converter (14); The digital output end of the AD/DA converter (14) is connected with the first input end of the comparator (15), and the output end of the memory (12) is connected with the second input end of the comparator (15); The output end of the comparator (15) is connected with the digital input end of the AD/DA converter (14); The analog output of the AD/DA converter (14) is connected to the phase-locked loop (20).
3. The control device (10) according to claim 2, characterized in that the digital output of the AD/DA converter (14) is connected to the input of the memory (12).
4. A control device (10) according to claim 2 or 3, characterized in that the comparator (15) is integrated in the AD/DA converter (14); Or the AD/DA converter (14) is integrated in the memory (12).
5. A control system of a phase locked loop, characterized in that the control system comprises a control device (10) of the phase locked loop according to any one of claims 1-4 and the phase locked loop (20) being connected to the control device (10).
6. A method of controlling a phase locked loop, the method comprising: Before the phase-locked loop is interrupted, acquiring a stored first working frequency, comparing the first working frequency with a second working frequency locked by the phase-locked loop, if the second working frequency is different from the first working frequency, acquiring characteristic data under the second working frequency, correspondingly storing the characteristic data under the second working frequency and the second working frequency, wherein the first working frequency is the working frequency locked before the phase-locked loop is operated, and correspondingly storing the characteristic data under the first working frequency; After the current work of the phase-locked loop is interrupted, if the phase-locked loop needs to lock the second working frequency again, inquiring the second working frequency from the stored first working frequency and the second working frequency, reading the characteristic data under the second working frequency stored corresponding to the second working frequency, and controlling the phase-locked loop to lock the second working frequency again based on the characteristic data under the second working frequency.
7. The method of claim 6, wherein controlling the phase-locked loop to re-lock the second operating frequency based on the characteristic data at the second operating frequency comprises: And charging a loop filter of the phase-locked loop based on the characteristic data at the second working frequency, so that the phase-locked loop is locked at the second working frequency again.
8. The method of claim 7, wherein the method further comprises: And collecting the characteristic data of the phase-locked loop in the process of charging the loop filter of the phase-locked loop based on the characteristic data at the second working frequency, and stopping charging the loop filter when the difference value between the collected characteristic data and the characteristic data at the second working frequency is smaller than a threshold value.
9. The method of claim 7, wherein the characteristic data at the second operating frequency is a tuning voltage value of the phase-locked loop at the locked second operating frequency; the charging the loop filter of the phase-locked loop based on the characteristic data at the second operating frequency includes: An analog current signal is generated based on the tuning voltage value, and a loop filter of the phase-locked loop is charged based on the analog current signal.
10. The method according to any one of claims 6-9, further comprising converting the characteristic data at the second operating frequency into a digital signal form suitable for storage after the collecting the characteristic data at the second operating frequency; The controlling the phase-locked loop to re-lock the second operating frequency based on the characteristic data at the second operating frequency includes controlling the phase-locked loop to re-lock the second operating frequency based on the characteristic data at the second operating frequency converted from a digital signal form to an analog signal form.

Description

Control device, system and method of phase-locked loop Technical Field The present application relates to the field of communications technologies, and in particular, to a control device, a system, and a method for a phase locked loop. Background In the field of communication technology, electronic devices typically use a PLL (Phase Locked Loop ) to lock on the frequency and phase of a clock signal to provide an accurate, stable clock source. In some applications, such as DDR (Double Data Rate) applications, PLL interrupt operation is controlled when a clock source is not needed. And controlling the PLL to resume operation until the clock source is needed again, so as to save power consumption. Since the PLL needs to be locked again in frequency and phase when the PLL is restored to operate, the process of locking the PLL with the frequency needs to take a long time, which may have a certain influence on the communication performance of the electronic device. Therefore, it is necessary to provide a control method of a phase locked loop so that the phase locked loop can be quickly relocked. Disclosure of Invention The embodiment of the application provides a control device, a system and a method of a phase-locked loop, which are used for enabling the phase-locked loop to be quickly locked again. The technical proposal is as follows. In one aspect, a control device of a phase-locked loop is provided, the control device comprises a collector, a memory and a controller, the input end of the collector is connected with the phase-locked loop, the output end of the collector is connected with the input end of the memory, the output end of the memory is connected with the input end of the controller, and the output end of the controller is connected with the phase-locked loop; The collector is configured to collect characteristic data of the phase-locked loop at the working frequency of the current working locking before the phase-locked loop is interrupted; a memory configured to store characteristic data at the operating frequency; and the controller is configured to read the characteristic data stored in the memory at the working frequency after the phase-locked loop is interrupted, and control the phase-locked loop to re-lock the working frequency based on the characteristic data at the working frequency if the phase-locked loop needs to re-lock the working frequency. In one possible implementation, the controller includes an AD (analog Digital)/DA (Digital analog) converter and a comparator, an output of the collector is connected to an analog input of the AD/DA converter, a Digital output of the AD/DA converter is connected to a first input of the comparator, an output of the memory is connected to a second input of the comparator, an output of the comparator is connected to a Digital input of the AD/DA converter, and an analog output of the AD/DA converter is connected to a phase-locked loop. In one possible implementation, the digital output of the AD/DA converter is connected to the input of the memory. In one possible implementation, the comparator is integrated in an AD/DA converter, or the AD/DA converter is integrated in memory. On the other hand, a control system of the phase-locked loop is provided, and the control system comprises a control device of any phase-locked loop and the phase-locked loop connected with the control device. In another aspect, a method for controlling a phase locked loop is provided, the method including: Before the phase-locked loop is interrupted, collecting characteristic data of the phase-locked loop at the working frequency locked by the current working, and storing the characteristic data of the phase-locked loop at the working frequency; After the phase-locked loop is interrupted, if the phase-locked loop needs to lock the working frequency again, the stored characteristic data at the working frequency is read, and the phase-locked loop is controlled to lock the working frequency again based on the characteristic data at the working frequency. In one possible implementation, controlling the phase-locked loop to relock the operating frequency based on the characteristic data at the operating frequency includes charging a loop filter of the phase-locked loop based on the characteristic data at the operating frequency to relock the operating frequency. In one possible implementation, the method further comprises the step of collecting characteristic data of the phase-locked loop in the process of charging the loop filter of the phase-locked loop based on the characteristic data at the working frequency, and stopping charging the loop filter when the difference between the collected characteristic data and the characteristic data at the working frequency is smaller than a threshold value. In one possible implementation, the characteristic data at the operating frequency is a tuning voltage value of the phase-locked loop at the locked operating frequency, and charging the l