CN-115248661-B - Copy commands for memory systems

Abstract

The present disclosure is directed to copy commands for memory systems. A method may include storing data associated with one or more first addresses within an address space in a memory system. The method may additionally include receiving a copy command for the data from a host for the memory system. The memory system may associate the data with one or more second addresses within the address space in response to the copy command.

Inventors

• C. M. Yu lunscog
• L Porcio

Assignees

• 美光科技公司

Dates

Publication Date

20260505

Application Date

20220426

Priority Date

20220411

Claims (20)

1. 1. A memory system, comprising: One or more memory devices, and Processing circuitry coupled with the one or more memory devices and configured to cause the memory system to: Storing, within the one or more memory devices, data associated with one or more first addresses within an address space; Receiving a copy command for the data for the one or more memory devices from a host, wherein the copy command includes a value representing a number of bytes, the number of bytes being a length of a copy parameter list associated with the copy command, the copy parameter list to be received by the memory system subsequent to receiving the copy command; Receiving the copy parameters list from the host after receiving the copy command, wherein the copy parameters list includes the one or more first addresses and one or more second addresses, and wherein the length of the copy parameters list is equal to the number of bytes represented by the value included in the copy command, and In response to the copy command, the data is associated with the one or more second addresses within the address space.
2. 2. The memory system of claim 1, wherein: The data comprising one or more data blocks, and The copy parameter list includes one or more block indicators each for a respective block of the one or more blocks.
3. 3. The memory system of claim 2, wherein a block indicator of the one or more block indicators comprises an indication of a respective start address for the respective block within the address space, a size indication of the respective block, or both.
4. 4. The memory system of claim 2, wherein the copy parameter list includes an indication of an amount of information allocated to the one or more block indicators.
5. 5. The memory system of claim 1, wherein the replication parameter list comprises an indication of an amount of information included in the replication parameter list, the amount of information excluding the indication of the amount.
6. 6. The memory system of claim 1, wherein the list of replication parameters includes an indication of a starting address within the one or more second addresses.
7. 7. The memory system of claim 6, wherein to associate the data with the one or more second addresses, the processing circuit is configured to cause the memory system to: the data is associated with a sequential set of addresses starting at the start address indicated by the replication parameter list.
8. 8. The memory system of claim 1, wherein the copy command comprises an operation code specific to the copy command.
9. 9. The memory system of claim 1, wherein the processing circuitry is configured to allow the memory system to transmit a busy state to the host for a limited duration after receiving the copy command.
10. 10. The memory system of claim 1, wherein the processing circuit is further configured to cause the memory system to: Reading the data from a first set of memory cells associated with the one or more first addresses in response to the copy command, and In response to the copy command, a copy of the data is written to a second set of memory cells associated with the one or more second addresses.
11. 11. The memory system of claim 10, wherein: The one or more second addresses including one or more second logical addresses, and Associating the data with the one or more second addresses includes updating one or more mapping tables within the memory system to associate the one or more second logical addresses with one or more second physical addresses corresponding to the second set of memory cells.
12. 12. The memory system of claim 10, wherein the data remains stored at the first set of memory cells after the copy of the data is written to the second set of memory cells.
13. 13. The memory system of claim 1, wherein: The one or more second addresses include one or more second logical addresses; The data is stored at a set of memory cells having one or more physical addresses prior to receiving the copy command, an Associating the data with the one or more second addresses includes updating one or more mapping tables within the memory system to associate the one or more second logical addresses with the one or more physical addresses.
14. 14. The memory system of claim 13, wherein the processing circuit is further configured to cause the memory system to: Continuing to store the data at the set of memory cells having the one or more physical addresses, wherein: the one or more first addresses including one or more first logical addresses, and After the data is associated with the one or more second addresses, the one or more mapping tables associate the one or more physical addresses with both the one or more second logical addresses and the one or more first logical addresses.
15. 15. A non-transitory computer-readable medium storing code comprising instructions that, when executed by one or more processors of an electronic device, cause the electronic device to: storing, in one or more memory devices, data associated with one or more first addresses within an address space; receiving a copy command for the data for the one or more memory devices from a host, wherein the copy command includes a value representing a number of bytes, the number of bytes being a length of a copy parameter list associated with the copy command, the copy parameter list to be received by a memory system subsequent to receiving the copy command; Receiving the copy parameters list from the host after receiving the copy command, wherein the copy parameters list includes the one or more first addresses and one or more second addresses, and wherein the length of the copy parameters list is equal to the number of bytes represented by the value included in the copy command, and In response to the copy command, the data is associated with the one or more second addresses within the address space.
16. 16. The non-transitory computer-readable medium of claim 15, wherein: The data comprising one or more data blocks, and The copy parameter list includes one or more block indicators each for a respective block of the one or more blocks.
17. 17. The non-transitory computer-readable medium of claim 16, wherein a block indicator of the one or more block indicators comprises an indication of a respective start address for the respective block within the address space, a size indication of the respective block, or both.
18. 18. The non-transitory computer-readable medium of claim 16, wherein the list of replication parameters comprises an indication of an amount of information allocated to the one or more block indicators.
19. 19. The non-transitory computer-readable medium of claim 15, wherein the replication parameter list comprises an indication of an amount of information included in the replication parameter list, the amount of information not comprising the indication of the amount.
20. 20. The non-transitory computer-readable medium of claim 15, wherein the list of replication parameters comprises an indication of a starting address within the one or more second addresses.

Description

Copy commands for memory systems Cross-reference to related applications This patent application claims priority from U.S. patent application Ser. No. 17/717,762 entitled "copy Command for memory System (COPY COMMAND FOR A MEMORY SYSTEM)" filed by Galenssual (Gyllenskog) et al at 2022, month 4, and 11, which claims the benefit of U.S. provisional patent application Ser. No. 63/180,441 entitled "copy Command for memory System (COPY COMMAND FOR A MEMORY SYSTEM)" filed by Galenssual at 2021, month 4, and 27, which are both assigned to the present assignee and expressly incorporated herein by reference in their entirety. Technical Field The technical field relates to copy commands for memory systems. Background Memory devices are widely used to store information in a variety of electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device to various states. For example, a binary memory cell may be programmed to one of two support states, often corresponding to a logic 1 or a logic 0. In some examples, a single memory cell may support more than two possible states, and a memory cell may store either of the two possible states. To access information stored by the memory device, the component may read or sense the state of one or more memory cells within the memory device. To store information, a component may write or program one or more memory cells within a memory device to respective states. There are various types of memory devices including magnetic hard disk, random Access Memory (RAM), read Only Memory (ROM), dynamic RAM (DRAM), synchronous Dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase Change Memory (PCM), 3-dimensional cross point memory (3D cross point), NOR, NAND memory devices, and the like. The memory device may be volatile or nonvolatile. Unless periodically updated by an external power source, volatile memory cells (e.g., DRAM cells) can lose their programmed state over time. Nonvolatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long period of time even in the absence of an external power source. Disclosure of Invention An apparatus is described. The apparatus may include one or more memory devices. The apparatus may also include a controller coupled with the one or more memory devices and configured to cause the apparatus to store data associated with one or more first addresses within an address space within the one or more memory devices, receive a copy command for the data for the one or more memory devices from a host, and associate the data with one or more second addresses within the address space in response to the copy command. A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to store data associated with one or more first addresses within an address space in one or more memory devices, receive a copy command for the data for the one or more memory devices from a host, and associate the data with one or more second addresses within the address space in response to the copy command. A method performed by a memory system including one or more memory devices is described. The method may include storing, within the one or more memory devices, data associated with one or more first addresses within an address space, receiving, from a host, a copy command for the one or more memory devices for the data, and associating, in response to the copy command, the data with one or more second addresses within the address space. An apparatus is described. The apparatus may include a controller configured to couple with a memory system. The controller may be configured to cause the apparatus to identify data associated with one or more first addresses within an address space associated with the memory system, transmit a copy command to the memory system, wherein the copy command instructs the memory system to associate the data with one or more second addresses within the address space, and transmit an access command for at least a portion of the data to the memory system after transmitting the copy command, wherein the access command is associated with a second address of the one or more second addresses. A non-transitory computer-readable medium storing code comprising instructions is described. The code comprising instructions may, when executed by a processor of an electronic device, cause the electronic device to identify data associated with one or more first addresses within an address space associated with a memory system, transmit a copy command to the memory system, wherein the copy command instructs the memory system to associate the data with one or more second addresses within