CN-115249507-B - Secure self-cleaning memory partition

Abstract

The present application is directed to secure self-cleaning memory partitioning. Systems, techniques, and devices are described herein in which data stored in a portion of a secure partition of memory is removable from the secure partition. In some examples, a portion of the secure partition may be allocated as self-cleaning memory such that data stored therein may be selectively removed in response to a logical address associated with the data being overwritten. In some cases, the data may be removed by programming the memory cells associated with the data to a particular voltage distribution. In some cases, the secure partition may include separate portions having different sets of operating parameters for access operations.

Inventors

• G. Carlo

Assignees

• 美光科技公司

Dates

Publication Date

20260505

Application Date

20220422

Priority Date

20210426

Claims (20)

1. 1. A method, comprising: configuring a first set of operating parameters for an access operation for a first portion of a secure partition of a memory device, the secure partition configured to store data for an authenticated system; Configuring a second set of operating parameters for an access operation for a second portion of the secure partition, the second set of operating parameters being different from the first set of operating parameters for the first portion of the secure partition; writing data to the second portion of the secure partition using the second set of operating parameters, and The data stored in the second portion of the secure partition is overwritten based at least in part on writing the data using the second set of operating parameters.
2. 2. The method of claim 1, wherein overwriting the data further comprises: second data is written to the second portion of the secure partition to cause each memory cell storing the data to stabilize at the same voltage distribution.
3. 3. The method as recited in claim 1, further comprising: Third data is written to the second portion of the secure partition at a location where the data is stored based at least in part on overwriting the data.
4. 4. The method as recited in claim 1, further comprising: writing second data to the first portion of the secure partition, wherein a first logic state is written to the first portion using a first write voltage, and Wherein writing the data to the second portion comprises: the first logic state is written to the second portion using a second write voltage that is different from the first write voltage.
5. 5. The method of claim 4, wherein a first voltage distribution of memory cells storing the first logic state in the first portion of the secure partition is different from a second voltage distribution of memory cells storing the first logic state in the second portion of the secure partition.
6. 6. The method of claim 4, wherein writing the second data to the first portion of the secure partition comprises: writing a second logic state to the first portion using a third write voltage, and Wherein writing the data to the second portion comprises: The second logic state is written to the second portion using the third write voltage.
7. 7. The method of claim 6, wherein a third voltage distribution of memory cells storing the second logic state in the first portion of the secure partition is the same as memory cells storing the second logic state in the second portion of the secure partition.
8. 8. The method as recited in claim 1, further comprising: Comparing a first charge of a first memory cell in the first portion with a first read reference voltage as part of a first read operation of the first portion, and A portion of a second read operation as the second portion compares a second charge of a second memory cell in the second portion with a second read reference voltage different from the first read reference voltage.
9. 9. The method of claim 1, wherein the secure partition comprises replay protected memory blocks.
10. 10. The method of claim 1, wherein a first operating parameter of the first set of operating parameters of the first portion of the secure partition comprises a first read reference voltage, and Wherein a second operating parameter of the second set of operating parameters of the second portion of the secure partition comprises a second read reference voltage that is greater than the first read reference voltage.
11. 11. The method of claim 1, wherein a first operating parameter of the first set of operating parameters of the first portion of the secure partition comprises a first write voltage to write a first logic state to a memory cell, and Wherein a second operating parameter of the second set of operating parameters of the second portion of the secure partition includes a second write voltage to write the first logic state to the memory cell and different from the first write voltage.
12. 12. The method of claim 1, wherein a counter is associated with the secure partition and configured to reduce a likelihood of success of a replay attack applied to the data stored in the secure partition.
13. 13. An apparatus, comprising: A memory device having a secure partition configured to store information for an authenticated system, wherein the secure partition comprises: A first portion configured to store a first set of operating parameters for an access operation, and A second portion configured to store a second set of operating parameters for the access operation, and The apparatus further comprises a controller associated with the memory device, wherein the controller is configured to cause the apparatus to: Writing data to the second portion of the secure partition of the memory device using the second set of operating parameters, and The data stored in the second portion of the secure partition of the memory device is overwritten based at least in part on writing the data using the second set of operating parameters.
14. 14. The apparatus of claim 13, wherein the controller is further configured to cause the apparatus to: second data is written to the second portion of the secure partition of the memory device to cause each memory cell storing the data to stabilize at the same voltage distribution.
15. 15. The apparatus of claim 13, wherein the controller is further configured to cause the apparatus to: Third data is written to the second portion of the secure partition at a location where the data is stored based at least in part on overwriting the data.
16. 16. The apparatus of claim 13, wherein the controller is further configured to cause the apparatus to: Writing second data to the first portion of the secure partition, wherein to write the second data to the first portion of the secure partition, the controller is further configured to cause the apparatus to write a first logic state to the first portion using a first write voltage, and Wherein to write the data to the second portion of the secure partition, the controller is further configured to cause the apparatus to write the first logical state to the second portion using a second write voltage different from the first write voltage.
17. 17. The apparatus of claim 13, wherein the controller is further configured to cause the apparatus to: Comparing a first charge of a first memory cell in the first portion with a first read reference voltage as part of a first read operation of the first portion, and A portion of a second read operation as the second portion compares a second charge of a second memory cell in the second portion with a second read reference voltage different from the first read reference voltage.
18. 18. The apparatus of claim 13, wherein: A first operating parameter of the first set of operating parameters of the first portion of the secure partition comprises a first read reference voltage, an A second operating parameter of the second set of operating parameters of the second portion of the secure partition includes a second read reference voltage that is greater than the first read reference voltage.
19. 19. The apparatus of claim 13, wherein: The first operating parameters of the first set of operating parameters of the first portion of the secure partition include a first write voltage to write a first logic state to a memory cell, an A second operating parameter of the second set of operating parameters of the second portion of the secure partition includes a second write voltage to write the first logic state to the memory cell and different from the first write voltage.
20. 20. A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to: configuring a first set of operating parameters for an access operation for a first portion of a secure partition of a memory device, the secure partition configured to store data for an authenticated system; Configuring a second set of operating parameters for an access operation for a second portion of the secure partition, the second set of operating parameters being different from the first set of operating parameters for the first portion of the secure partition; writing data to the second portion of the secure partition using the second set of operating parameters, and The data stored in the second portion of the secure partition is overwritten based at least in part on writing the data using the second set of operating parameters.

Description

Secure self-cleaning memory partition Cross reference This patent application claims priority from U.S. patent application Ser. No. 17/240,940 entitled "SECURE SELF-cleaning memory partition (SECURE SELF-PURGING MEMORY PARTITIONS)" filed by Cariello (Cariello) at month 26 of 2021, which is expressly incorporated herein by reference in its entirety. Technical Field The technical field relates to secure self-cleaning memory partitioning. Background Memory devices are widely used to store information in a variety of electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device to various states. For example, a binary memory cell may be programmed to one of two support states, which generally corresponds to a logic 1 or a logic 0. In some examples, a single memory cell may support more than two possible states, and a memory cell may store either of the two possible states. To access information stored by the memory device, the component may read or sense the state of one or more memory cells within the memory device. To store information, a component may write or program one or more memory cells within a memory device to respective states. There are various types of memory devices including magnetic hard disk, random Access Memory (RAM), read Only Memory (ROM), dynamic RAM (DRAM), synchronous Dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase Change Memory (PCM), 3-dimensional cross point memory (3D cross point), NOR and NAND (NAND) memory devices, and the like. The memory device may be volatile or nonvolatile. Unless periodically updated by an external power source, volatile memory cells (e.g., DRAM cells) can lose their programmed state over time. Nonvolatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long period of time even in the absence of an external power source. Disclosure of Invention A method is described. The method may include configuring a first set of operating parameters for an access operation for a first portion of a secure partition of a memory device, the secure partition configured to store data for an authenticated system, configuring a second set of operating parameters for an access operation for a second portion of the secure partition, the second set of operating parameters being different from the first set of operating parameters for the first portion of the secure partition, writing data to the second portion of the secure partition using the second set of operating parameters, and overwriting the data stored in the second portion of the secure partition based at least in part on writing the data using the second set of operating parameters. An apparatus is described. The apparatus may include a memory device having a secure partition configured to store information for an authenticated system, wherein the secure partition includes a first portion configured to store a first set of operating parameters for an access operation and a second portion configured to store a second set of operating parameters for an access operation. The apparatus may also include a controller associated with the memory device, wherein the controller is configured to cause the apparatus to write data to the second portion of the secure partition of the memory device using the second set of operating parameters, and overwrite the data stored in the second portion of the secure partition of the memory device based at least in part on writing the data using the second set of operating parameters. A non-transitory computer-readable medium storing code is described. The code may include instructions executable by a processor to configure a first set of operating parameters for an access operation for a first portion of a secure partition of a memory device, the secure partition configured to store data for an authenticated system, configure a second set of operating parameters for an access operation for a second portion of the secure partition, the second set of operating parameters being different from the first set of operating parameters for the first portion of the secure partition, write data to the second portion of the secure partition using the second set of operating parameters, and overwrite the data stored in the second portion of the secure partition based at least in part on writing the data using the second set of operating parameters. Drawings FIG. 1 illustrates an example of a system supporting secure self-cleaning memory partitioning according to examples disclosed herein. FIG. 2 illustrates an example of a memory device supporting secure self-cleaning memory partitions according to examples disclosed herein. Fig. 3, 4A, 4B, and 4C illustrate example distribution graphs supporting secure self-cleaning memory partitioning according to examples disclosed herei