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CN-115249693-B - Method of manufacturing a microelectronic device and related microelectronic device, tool and apparatus

CN115249693BCN 115249693 BCN115249693 BCN 115249693BCN-115249693-B

Abstract

Methods of fabricating microelectronic devices, and related microelectronic devices, tools, and apparatus, including microelectronic devices, may have side surfaces that each include a first portion and a second portion. The first portion can have a highly irregular surface topography extending from an adjacent surface of the microelectronic device. The second portion can have a less rough surface extending from the first portion to an opposing surface of the microelectronic device. Methods of forming microelectronic devices can include generating dislocations in a wafer by implanting ions in streets between the one or more microelectronic devices, and cleaving the wafer in response to stress concentrating faults in the vicinity of the dislocations via application of heat, tension, or a combination thereof. Related packages and methods are also disclosed.

Inventors

  • A. M. Bailis
  • B.P. Watts

Assignees

  • 美光科技公司
  • 美光科技公司

Dates

Publication Date
20260421
Application Date
20220427
Priority Date
20210427

Claims (20)

  1. 1. A microelectronic device, comprising: A semiconductor material comprising an active surface and a back surface opposite the active surface; A side surface of the semiconductor material extending between the active surface and the back surface and comprising: A first portion having a highly irregular surface topography comprising residual ions, the highly irregular surface topography extending from one of the active surface and the rear surface of the microelectronic device a distance of between 2 μm and 6 μm, and A second portion that does not include the residual ions, which extends from the first portion to the other of the active surface and the rear surface, having a less-than-flat surface.
  2. 2. The microelectronic device of claim 1, further comprising an active region comprising an integrated circuit laterally recessed from the side surface above the active surface.
  3. 3. The microelectronic device of claim 2, further comprising a barrier region peripherally positioned between the active region and the side surface.
  4. 4. The microelectronic device of claim 3, wherein the barrier region is formed of a material selected to substantially prevent diffusion of a material different from the semiconductor material to the active region.
  5. 5. The microelectronic device of claim 3, wherein the barrier region is formed of a material selected from the group consisting of tungsten, titanium, cobalt, ruthenium, tantalum nitride, indium oxide, tungsten nitride, and titanium nitride.
  6. 6. The microelectronic device of claim 2, further comprising residual implanted ions adjacent to the first portion of the side surface.
  7. 7. The microelectronic device of claim 6, wherein the residual implanted ions comprise one or more of boron, phosphorus, arsenic, helium, and hydrogen.
  8. 8. The microelectronic device of claim 7, wherein the residual implanted ions comprise one of hydrogen or helium from the active surface or the rear surface at a depth adjacent to the first portion and one of boron, phosphorus, or arsenic from the same surface as the hydrogen at a lesser depth adjacent to the first portion.
  9. 9. The microelectronic device of any of claims 1-8, wherein the highly irregular surface topography comprises spot damage caused by an ion implantation process.
  10. 10. The microelectronic device of any of claims 1-8, wherein the less highly uneven surface comprises a flat surface with intermittent fracture lines.
  11. 11. The microelectronic device of any of claims 1-8, wherein a distance between the active surface and the rear surface is less than 30 micrometers (μιη).
  12. 12. A microelectronic package, comprising: one or more microelectronic devices, each comprising: a side surface of a semiconductor material, and comprising: a first portion having a highly irregular surface topography, the first portion comprising one or more point defects and dislocations extending from an adjacent major surface of the microelectronic device a distance of between 2 μm and 6 μm, and A second portion that does not include the point defects and dislocations, is adjacent to the first portion, and has a less-rough surface.
  13. 13. The microelectronic package of claim 12, wherein the highly irregular surface topography exhibits point damage in response to an ion implantation process.
  14. 14. The microelectronic package of claim 12, wherein the less highly uneven surface includes a flat surface with intermittent fracture lines.
  15. 15. The microelectronic package of any of claims 12-14, wherein the highly irregular surface topography is an adjacent portion of the semiconductor material that includes implanted ions of one or more of hydrogen, helium, boron, phosphorus, and arsenic.
  16. 16. A method of fabricating a microelectronic device, the method comprising: forming a microelectronic device on an active surface of a wafer; securing the wafer to a carrier wafer; implanting ions to induce dislocations in semiconductor material of the wafer along streets between the microelectronic devices, the dislocations extending from one of the active and rear surfaces of the wafer to a distance between 2 μm and 6 μm; Thinning the wafer to 30 micrometers (μm) or less, and The wafer is heated to form a crack along the streets from a stress concentration proximate to the dislocations.
  17. 17. The method of claim 16, wherein implanting ions comprises implanting ions through a mask having openings substantially aligned with the vias between the microelectronic devices.
  18. 18. The method of claim 17, wherein the mask comprises the same mask as is used to fabricate features of the microelectronic device.
  19. 19. The method of claim 17, wherein the mask comprises a reusable mask coupled to a face of an implantation tool or within a chamber of an implantation tool.
  20. 20. The method of any one of claims 16-19, comprising implanting ions from an active side of the wafer along the vias between the microelectronic devices.

Description

Method of manufacturing a microelectronic device and related microelectronic device, tool and apparatus Priority claim The present application claims the benefit of the applicant's application date of U.S. patent application Ser. No. 17/241,386 to App. No. 2021, 4, 27, the disclosure of which is hereby incorporated by reference in its entirety, as well as related microelectronic devices, tools and apparatus (METHOD OF FABRICATING MICROELECTRONIC DEVICES AND RELATED MICROELECTRONIC DEVICES,TOOLS,AND APPARATUS)". Technical Field Embodiments of the present disclosure relate to a method of manufacturing a microelectronic device. In particular, embodiments relate to methods of separating wafers including arrays of microelectronic device locations into individual microelectronic devices, and related microelectronic devices, tools, and apparatus. Background As the performance of electronic devices and systems increases, there is an associated need to improve the performance of the microelectronic components of such systems while maintaining or even shrinking the apparent dimensions (i.e., length, width, and height) of the microelectronic devices or assemblies. Such requirements are typically, but not exclusively, associated with mobile devices and high performance devices. To maintain or reduce the footprint and height of component assemblies in the form of microelectronic devices (e.g., semiconductor die), three-dimensional (3D) assemblies of stacked components equipped with so-called Through Silicon Vias (TSVs) for vertical electrical (i.e., signal, power, ground/bias) communication between stacked components have become more common, which combine a reduction in component thickness with the adoption of pre-formed dielectric films in bond wires (i.e., spaces between stacked components) to reduce bond wire thickness while increasing bond wire uniformity. Such dielectric films include, for example, so-called non-conductive films (NCF) and wafer level primers (WLUF), such terms being commonly used interchangeably. While effective in reducing the height of 3D microelectronic device assemblies, reducing the thickness of microelectronic devices, such as semiconductor dies, to about 50 μm or less (e.g., 30 μm, 20 μm) increases device vulnerability and susceptibility to cracking under stress, particularly compressive (i.e., impact) stress and bending stress. Reducing bond wire thickness may also exacerbate the vulnerability of such extremely thin microelectronic devices because thin dielectric materials (e.g., NCF) in the bond wires may no longer provide any cushioning effect or the ability to accommodate particulate contaminants in the bond wires when, for example, the devices are stacked on another device to form a 3D assembly. Non-limiting examples of microelectronic device assemblies including stacked microelectronic devices that may suffer from stress induced cracking include assemblies of semiconductor memory dies, either alone or in combination with other die functions (e.g., logic), including so-called high bandwidth memory (HBMx), hybrid Memory Cube (HMC), and chip-to-wafer (C2W) assemblies. In addition, as the demand for microelectronic devices increases, so does the demand for low cost microelectronic devices, thereby promoting a continued increase in circuit density per wafer and devices. The cost of producing microelectronic devices can be reduced by increasing the efficiency of the process, increasing the yield of microelectronic devices per wafer per respective process, and reducing losses (e.g., due to circuit failure, physical die cracking, micro-cracking, and cracking, etc.). Reducing the cost of microelectronic devices may in turn reduce the cost of associated electronic assemblies and systems incorporating such microelectronic devices. In some cases, reducing the cost of the microelectronic device may also enable an increase in performance of the associated electronic device without excessive cost. Disclosure of Invention Embodiments of the present disclosure may include microelectronic devices. The microelectronic device can include a semiconductor material including an active surface and a rear surface opposite the active surface. The microelectronic device can further include side surfaces of semiconductor material extending between the active surface and the rear surface. The side surface may include a first portion having a highly irregular surface topography extending from one of the active surface and the back surface of the microelectronic device a distance between about 2 μm and about 6 μm. The side surface may further include a second portion having a less rough surface extending from the first portion to the other of the active surface and the rear surface. Another embodiment of the present disclosure may include a microelectronic package. The microelectronic package may include one or more microelectronic devices. Each microelectronic device can include a side surface of semiconductor mate