CN-115292214-B - Page table prediction method, storage access operation method, electronic device and electronic equipment

CN115292214BCN 115292214 BCN115292214 BCN 115292214BCN-115292214-B

Abstract

A page table walk method, a memory access operation method, an electronic device and an electronic apparatus. The page table prediction method comprises the steps of obtaining a target virtual page number of a target virtual page with a first granularity where a target virtual address needing page table prediction is located, responding to at least one second table item to comprise a reference merging table item marked as available for prediction, wherein the target virtual page and a second granularity reference virtual page corresponding to the reference merging table item are located in an extended virtual page with the same third granularity, predicting to obtain a predicted physical page address corresponding to the target virtual page number based on the target virtual address and a physical page address corresponding to the reference virtual page number of the reference virtual page, merging the reference merging table item by X sub-table items which are consecutive in sequence, and corresponding to X physical pages corresponding to the sequence of the X sub-table items which are consecutive in sequence. The method improves the accuracy of address prediction and improves the utilization rate of the TLB.

Inventors

XU CUIPING

Assignees

海光信息技术股份有限公司

Dates

Publication Date: 20260512
Application Date: 20220811

Claims (17)

1. A page table walk method for a translation look-aside buffer, wherein the translation look-aside buffer comprises a plurality of first-granularity first entries and at least one second-granularity second entry, each of the at least one second entry is merged with a plurality of first-granularity sub-entries, The method comprises the following steps: acquiring a target virtual page number of a target virtual page with a first granularity where a target virtual address needing to be subjected to page table prediction is located; In response to the at least one second entry including a reference merge entry marked as available for prediction and the target virtual page being located within the same third granularity of extended virtual pages as a reference virtual page of a second granularity to which the reference merge entry corresponds, predicting a predicted physical page address to which the target virtual page number corresponds based on the target virtual address and a physical page address to which a reference virtual page number of the reference virtual page corresponds, Wherein the reference merging table entry is obtained by merging X sub-table entries which are consecutive in sequence, X physical pages corresponding to the sequence of the X sub-table entries which are consecutive in sequence are corresponding to each other, the third granularity is Y times of the second granularity, X, Y is an integer larger than 1, Wherein the third granularity is 2k bits, k is an integer greater than 1, Based on the target virtual address and a physical page address corresponding to a reference virtual page number of the reference virtual page, predicting to obtain a predicted physical page address corresponding to the target virtual page number includes: obtaining the highest bit to the kth bit of the predicted physical page address from the highest bit to the kth bit of the physical page address corresponding to the reference virtual page number; And setting the k-1 bit to the 0 th bit of the physical page address corresponding to the target virtual page number as the k-1 bit to the 0 th bit of the predicted physical page address.
2. The page table walk method of claim 1, wherein the second granularity is 2n times the first granularity, the third granularity is 2m times the second granularity, and m and n are positive integers.
3. The page table walk method of claim 1, further comprising: determining whether the reference merge table marked as available for prediction is included in the at least one second table entry.
4. The page table walk method of claim 1, further comprising: And judging whether the target virtual page and the reference virtual page of the second granularity corresponding to the reference merging table item are positioned in the extended virtual page of the same third granularity.
5. The page table walk method of claim 1, wherein each of the plurality of sub-entries represents a correspondence of a virtual page of a first granularity to a physical page of a first granularity, each of the at least one second entry represents a correspondence of a virtual page of a second granularity to a physical page of a second granularity, The method further comprises the steps of: And combining the sub-entries into one second table entry in response to a plurality of virtual pages of the first granularity being located within a virtual page of the same second granularity and a plurality of physical pages of the first granularity being located within a physical page of the same second granularity.
6. A method of storage access operation, comprising: Acquiring a target virtual address of object data used by a memory access instruction; Querying a translation look-up buffer using the target virtual address; In response to the target virtual address querying the translation look-up buffer miss, performing page table prediction using the target virtual address to obtain a predicted physical page address; Using the predicted physical page address to obtain a predicted target physical address corresponding to the target virtual address; subsequent operations required by the access instruction are performed using the predicted target physical address, Wherein the translation look-aside buffer comprises a plurality of first-granularity first table entries and at least one second-granularity second table entry, each of the at least one second table entry is obtained by combining a plurality of first-granularity sub-entries, Performing page table walk using the target virtual address, comprising: Acquiring a target virtual page number of a target virtual page with a first granularity where the target virtual address is located; In response to the at least one second entry including a reference merge entry marked as available for prediction and the target virtual page being located within the same third granularity of extended virtual pages as a reference virtual page of a second granularity to which the reference merge entry corresponds, predicting a predicted physical page address to which the target virtual page number corresponds based on the target virtual address and a physical page address to which a reference virtual page number of the reference virtual page corresponds, Wherein the reference merging table entry is obtained by merging X sub-table entries which are consecutive in sequence, X physical pages corresponding to the sequence of the X sub-table entries which are consecutive in sequence are corresponding to each other, the third granularity is Y times of the second granularity, X, Y is an integer larger than 1, Wherein the third granularity is 2k bits, k is an integer greater than 1, Based on the target virtual address and a physical page address corresponding to a reference virtual page number of the reference virtual page, predicting to obtain a predicted physical page address corresponding to the target virtual page number includes: obtaining the highest bit to the kth bit of the predicted physical page address from the highest bit to the kth bit of the physical page address corresponding to the reference virtual page number; And setting the k-1 bit to the 0 th bit of the physical page address corresponding to the target virtual page number as the k-1 bit to the 0 th bit of the predicted physical page address.
7. The memory access operation method of claim 6, wherein performing subsequent operations required by the memory access instruction using the predicted target physical address comprises: querying at least one level of private cache using the predicted target physical address; Acquiring data corresponding to the predicted target physical address from the at least one level private cache in response to querying the at least one level private cache hit, or And in response to querying the at least one level of private cache failure, suspending the subsequent operation.
8. The method of storage access operations of claim 7, wherein the at least one level of private cache comprises an L1 cache, or a combination of the L1 cache and an L2 cache.
9. The storage access operation method according to claim 6, further comprising: In the process of carrying out the follow-up operation by using the predicted target physical address, carrying out page table browsing operation by using the target virtual address in parallel and obtaining an actual target physical page address corresponding to the target virtual address; In response to the predicted physical page address and the actual target physical page address being the same, confirming success of page table prediction, or In response to the predicted physical page address and the actual target physical page address being different, confirming a page table prediction failure, undoing the subsequent operation that has been performed using the predicted target physical address.
10. The memory access operation method of claim 9, wherein the memory access instruction is marked as the confirmed page table walk success in response to the confirmed page table walk success.
11. The storage access operation method according to claim 6, further comprising, after obtaining the predicted target physical address corresponding to the target virtual address: For the memory access instruction, the target virtual address and the predicted target physical address are saved, and in the subsequent operation, the memory access instruction is marked as using the predicted target physical address.
12. The memory access operation method according to claim 11, wherein for the memory access instruction, at least one of the following parameters is set: a first parameter for identifying whether to use the predicted target physical address; a second parameter for identifying whether the physical address used for the subsequent operation is legal; and a third parameter for identifying whether page table walk is confirmed to be successful.
13. A storage management device, comprising: the management unit and the translation look-aside buffer, Wherein the translation look-aside buffer is configured to manage a plurality of first-granularity first entries and at least one second-granularity second entry, each of the at least one second entry being merged from a plurality of first-granularity sub-entries; The management unit is configured to obtain target virtual page number of target virtual page with first granularity where target virtual address needing page table prediction is located, and The management unit is further configured to, in response to the at least one second entry including a reference merge table marked as available for prediction and the target virtual page being located within an extended virtual page of the same third granularity as a reference virtual page of a second granularity corresponding to the reference merge table, predict a predicted physical page address corresponding to the target virtual page number based on the target virtual address and a physical page address corresponding to a reference virtual page number of the reference virtual page, Wherein the reference merging table entry is obtained by merging X sub-table entries which are consecutive in sequence, X physical pages corresponding to the sequence of the X sub-table entries which are consecutive in sequence are also corresponding to the sequence, the third granularity is Y times of the second granularity, X, Y is an integer larger than 1, Wherein the third granularity is 2k bits, k is an integer greater than 1, Based on the target virtual address and a physical page address corresponding to a reference virtual page number of the reference virtual page, predicting to obtain a predicted physical page address corresponding to the target virtual page number includes: obtaining the highest bit to the kth bit of the predicted physical page address from the highest bit to the kth bit of the physical page address corresponding to the reference virtual page number; And setting the k-1 bit to the 0 th bit of the physical page address corresponding to the target virtual page number as the k-1 bit to the 0 th bit of the predicted physical page address.
14. An electronic device, comprising: a control unit, and The storage management device of claim 13; The control unit is configured to obtain the target virtual address of object data used by a memory access instruction, query the translation look-up buffer by using the target virtual address, respond to the target virtual address to query the translation look-up buffer and miss, obtain the predicted physical page address obtained by page table prediction of the memory management device through the target virtual address, obtain a predicted target physical address corresponding to the target virtual address by using the predicted physical page address, and perform subsequent operations required by the memory access instruction by using the predicted target physical address.
15. The electronic device of claim 14, further comprising: at least one level of private cache; The control unit is further configured to query the at least one level of private cache by using the predicted target physical address, obtain data corresponding to the predicted target physical address from the at least one level of private cache in response to querying the at least one level of private cache hit, or suspend the subsequent operation in response to querying the at least one level of private cache failure.
16. The electronic device of claim 14, wherein the memory management device further comprises a page table walk unit, The memory management device is configured to allow the page table walk unit to conduct page table walk operation using the target virtual address and acquire an actual target physical page address corresponding to the target virtual address, The control unit is further configured to confirm that page table prediction was successful in response to the predicted physical page address and the actual target physical page address being the same, or to confirm that page table prediction was failed in response to the predicted physical page address and the actual target physical page address being different, and to undo the subsequent operation that has been performed using the predicted target physical address.
17. An electronic device, comprising: the electronic device of any of claims 14-16.

Description

Page table prediction method, storage access operation method, electronic device and electronic equipment Technical Field Embodiments of the present disclosure relate to a page table walk method, a memory access operation method, an electronic device, and an electronic apparatus. Background In the field of computer technology, a programmer may write a program using an arbitrary Virtual Address (VA) within a system specification range instead of a physical Address, and an Address used when a central processing unit (Central Processing Unit, CPU) executes an application program is a Virtual Address. Typically, different processes running in the system are assigned different virtual address spaces, each of which covers a large area. For example, when allocating memory to a process and accessing memory by a process, virtual addresses need to be mapped to physical addresses (PHYSICAL ADDRESS, PA), which are the actual physical memory access addresses. Virtual addresses and physical addresses are managed through Page tables (Page tables). The CPU will determine the virtual page Number (Virtual Page Number, VPN) to the physical memory based on the virtual address transmitted by the program, read the page table, find the physical page Number (PHYSICAL PAGE Number, PPN) corresponding to the virtual page Number in the page table, and then access the actual physical memory address according to the physical page Number. That is, the CPU must access physical memory at least twice throughout the process. In order to reduce the number of times the CPU accesses physical memory, a translation lookaside buffer (Translation Lookaside Buffer, TLB), also referred to as a page table cache, a translation bypass cache, etc., is introduced into the processor core. Disclosure of Invention At least one embodiment of the present disclosure provides a page table prediction method, which completes prediction of a virtual address to physical address translation relationship based on a page table merging technique, and improves accuracy of address prediction, thereby reducing delay caused by page table traversal due to TLB capacity limitation. The embodiment of the disclosure provides a page table prediction method, which is used for a translation backup buffer, wherein the translation backup buffer comprises a plurality of first-granularity first table entries and at least one second-granularity second table entry, each of the at least one second table entry is obtained by merging a plurality of first-granularity sub-table entries, the method comprises the steps of obtaining a target virtual page number of a target virtual page of a first granularity where a target virtual address needs to be subjected to page table prediction, responding to the at least one second table entry to comprise a reference merging table entry marked as available for prediction, the target virtual page and a second-granularity reference virtual page corresponding to the reference merging table entry are located in an extended virtual page of the same third granularity, predicting to obtain a predicted physical page address corresponding to the target virtual page number based on the target virtual address and a physical page address corresponding to the reference virtual page number, wherein the reference merging table entry is obtained by merging sequentially consecutive X sub-table entries, and the sequentially consecutive X sub-table entries also correspond to the third-granularity Y is a sequentially greater than X, Y, and the sequentially consecutive X sub-table entries are sequentially greater than 391. For example, in the page table prediction method provided in at least one embodiment of the present disclosure, the second granularity is 2 n times the first granularity, the third granularity is 2 m times the second granularity, and m and n are positive integers. For example, at least one embodiment of the present disclosure provides for a page table walk method further comprising determining whether the reference merge table entry marked as available for walk prediction is included in the at least one second table entry. For example, the page table prediction method provided in at least one embodiment of the present disclosure further includes determining whether the target virtual page and the reference virtual page of the second granularity corresponding to the reference merge table entry are located in an extended virtual page of the same third granularity. For example, in the page table prediction method provided in at least one embodiment of the present disclosure, each of the plurality of sub-entries represents a correspondence between a virtual page of a first granularity and a physical page of a first granularity, and each of the at least one second entry represents a correspondence between a virtual page of a second granularity and a physical page of a second granularity, and the method further includes merging the plurality of sub-entries into