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CN-115295038-B - Semiconductor memory with temperature dependence

CN115295038BCN 115295038 BCN115295038 BCN 115295038BCN-115295038-B

Abstract

The invention provides a semiconductor memory having temperature dependence. The semiconductor memory includes a memory array, a temperature sensor circuit, and a pump circuit. The temperature sensor circuit is used for providing a temperature dependent signal. The pump circuit is coupled to the temperature sensor circuit and the memory array. The pump circuit is used for outputting the output voltage of the charge pump to the memory array according to the temperature dependent signal. The charge pump output voltage is determined based on the temperature dependent signal.

Inventors

  • SETOGAWA JUN

Assignees

  • 力晶积成电子制造股份有限公司

Dates

Publication Date
20260505
Application Date
20210709
Priority Date
20210503

Claims (19)

  1. 1. A semiconductor memory having temperature dependence, comprising: A memory array; a temperature sensor circuit for providing a temperature dependent signal, and A pump circuit coupled to the temperature sensor circuit and the memory array and configured to output a charge pump output voltage to the memory array according to the temperature dependent signal, Wherein the charge pump output voltage is determined based on the temperature dependent signal, Wherein the pump circuit comprises: a voltage comparator circuit coupled to the temperature sensor circuit and configured to receive a reference voltage and the charge pump output voltage, and A charge pump coupled to the voltage comparator circuit, wherein the voltage comparator circuit outputs a pump start signal to the charge pump according to the reference voltage and a feedback voltage corresponding to the charge pump output voltage, and the charge pump outputs the charge pump output voltage according to the pump start signal, Wherein the voltage comparator circuit comprises: a first resistor, wherein a first end of the first resistor is coupled to the charge pump output voltage and a second end of the first resistor is coupled to a circuit node; A second resistor, wherein a first end of the second resistor is coupled to the circuit node and a second end of the second resistor is coupled to a ground voltage, and A first comparator, wherein a first input of the first comparator is coupled to the circuit node to receive the feedback voltage, a second input of the first comparator receives the reference voltage, and an output of the first comparator outputs the pump enable signal, Wherein the reference voltage or the feedback voltage is determined according to the temperature dependent signal, Wherein the temperature sensor circuit comprises: A temperature sensor for outputting logic signals, and A voltage selector coupled to the temperature sensor and the second input terminal of the first comparator for receiving the logic signal, and A voltage dividing resistor coupled to the voltage selector for generating a plurality of divided voltages according to a high voltage level and a low voltage level, Wherein the voltage selector generates the reference voltage as the temperature dependent signal provided to the first comparator according to the plurality of divided voltages and the logic signal.
  2. 2. The temperature-dependent semiconductor memory of claim 1, wherein the temperature sensor determines that a temperature sensing voltage is between two of a plurality of threshold voltages to output the logic signal having a specific logic code sequence.
  3. 3. The temperature-dependent semiconductor memory according to claim 2, wherein the temperature-sensing voltage is inversely related to a temperature sensed via the temperature sensor.
  4. 4. The temperature-dependent semiconductor memory of claim 1, wherein the temperature sensor circuit comprises: The temperature sensor is coupled to the second input end of the first comparator and is used for providing an analog signal as the reference voltage.
  5. 5. The semiconductor memory having temperature dependency of claim 4, wherein the temperature sensor comprises: A second comparator, wherein a first input of the second comparator is coupled to a constant voltage; a third resistor, wherein a first end of the third resistor is coupled to a temperature sensing voltage and a second end of the third resistor is coupled to a second input of the second comparator, and A fourth resistor, wherein a first end of the fourth resistor is coupled to the second input of the second comparator, and a second end of the fourth resistor is coupled to an output of the second comparator, Wherein the output of the second comparator outputs the analog signal.
  6. 6. The temperature-dependent semiconductor memory according to claim 5, wherein the temperature-sensing voltage is inversely related to a temperature sensed via the temperature sensor.
  7. 7. The temperature-dependent semiconductor memory of claim 1, wherein the first resistor and the second resistor are variable resistors, and the temperature sensor circuit comprises: And a temperature sensor coupled to the first resistor and the second resistor, the temperature sensor configured to output a logic signal as the temperature dependent signal to adjust a first resistance value of the first resistor and a second resistance value of the second resistor to correspondingly adjust the feedback voltage.
  8. 8. The temperature-dependent semiconductor memory of claim 7, wherein the temperature sensor determines that a temperature sensing voltage is between two of a plurality of threshold voltages to output the logic signal having a specific logic code sequence.
  9. 9. The temperature-dependent semiconductor memory of claim 8, wherein the temperature-sensing voltage is inversely related to a temperature sensed via the temperature sensor.
  10. 10. The temperature-dependent semiconductor memory of claim 1, wherein the charge pump output voltage is inversely related to a temperature sensed via the temperature sensor circuit.
  11. 11. The temperature-dependent semiconductor memory of claim 1, wherein the pump circuit outputs the charge pump output voltage to the memory array as a memory control voltage.
  12. 12. The temperature-dependent semiconductor memory of claim 1, wherein the pump circuit outputs the charge pump output voltage to a sense amplifier of the memory array as a control signal voltage for a transistor in the sense amplifier.
  13. 13. The temperature-dependent semiconductor memory of claim 1, wherein the pump circuit outputs the charge pump output voltage to a sense amplifier of the memory array as a reverse bias of a transistor in the sense amplifier.
  14. 14. The temperature-dependent semiconductor memory according to claim 1, wherein the pump circuit outputs the charge pump output voltage to an equalization control circuit of the memory array as an equalization voltage or a reverse bias voltage of a transistor in the equalization control circuit.
  15. 15. The temperature-dependent semiconductor memory of claim 1, wherein the pump circuit outputs the charge pump output voltage to an equalization control circuit of the memory array as a reverse bias of a transistor in the equalization control circuit.
  16. 16. The temperature-dependent semiconductor memory of claim 1, wherein the pump circuit outputs the charge pump output voltage to a word line voltage of a memory cell of the memory array as a word line.
  17. 17. The temperature-dependent semiconductor memory of claim 1, wherein the pump circuit outputs the charge pump output voltage to memory cells of the memory array as a reverse bias of transistors coupled to word lines.
  18. 18. The temperature-dependent semiconductor memory of claim 1, wherein the pump circuit outputs the charge pump output voltage to the memory array as a switching voltage for a data bus.
  19. 19. The temperature-dependent semiconductor memory of claim 1, wherein the pump circuit outputs the charge pump output voltage to the memory array as a reverse bias of a transistor coupled to a data bus.

Description

Semiconductor memory with temperature dependence Technical Field The present invention relates to a memory device, and in particular, to a semiconductor memory having temperature dependency. Background For a general semiconductor memory, the output voltage of a charge pump in the semiconductor memory is constant. On the other hand, the size of the latest semiconductors is continuously shrinking, and the designs of memory forms are becoming more and more diversified. Therefore, a general semiconductor memory may have a wide range regarding temperature variation and a rapid temperature variation. That is, the general semiconductor memory has a problem that it is difficult to optimize a control voltage of the semiconductor memory in the case of a temperature change and the memory function may be further adversely affected. Accordingly, the following provides several embodiments of solutions as to how to provide a new semiconductor memory with temperature dependence. Disclosure of Invention The present invention is directed to a semiconductor memory having temperature dependency, and an operating voltage in a memory array can be automatically adjusted according to a temperature change. The semiconductor memory with temperature dependence of the present invention includes a memory array, a temperature sensor circuit, and a pump circuit. The temperature sensor circuit is used for providing a temperature dependent signal. The pump circuit is coupled to the temperature sensor circuit and the memory array. The pump circuit is used for outputting the output voltage of the charge pump to the memory array according to the temperature dependent signal. The charge pump output voltage is determined based on the temperature dependent signal. Based on the above, according to the semiconductor memory having temperature dependency of the present invention, the semiconductor memory can adjust the charge pump output voltage based on the current temperature of the semiconductor memory, wherein the charge pump output voltage can be used as the relevant internal operation voltage in the semiconductor memory. Therefore, the semiconductor memory of the present invention can effectively reduce the influence of temperature on the semiconductor memory. In order that the foregoing will be more readily understood, several embodiments are described in detail below with reference to the accompanying drawings. Drawings Fig. 1 is a schematic circuit diagram of a semiconductor memory according to an embodiment of the present invention. Fig. 2 is a schematic circuit diagram of a voltage comparator circuit according to an embodiment of the present invention. Fig. 3 is a schematic circuit diagram of a semiconductor memory of a first embodiment of the present invention. FIG. 4 is a diagram illustrating a relationship between logic signals and temperature according to an embodiment of the present invention. Fig. 5 is a schematic circuit diagram of a semiconductor memory of a second embodiment of the present invention. Fig. 6 is a schematic circuit diagram of the internal circuitry of a temperature sensor according to an embodiment of the present invention. FIG. 7 is a diagram illustrating a relationship between temperature sensing voltage and temperature according to an embodiment of the invention. Fig. 8 is a schematic circuit diagram of a semiconductor memory of a third embodiment of the present invention. Fig. 9 is a schematic circuit diagram of a sense amplifier control circuit and an equalization control circuit of a semiconductor memory according to an embodiment of the present invention. Fig. 10A is a schematic diagram showing a plurality of operation voltages of the sense amplifier control circuit and the equalization control circuit with temperature. Fig. 10B to 10D are schematic diagrams illustrating the temperature variation of the operating voltages according to the embodiment of fig. 9. FIG. 11 is a schematic circuit diagram of a word line circuit of a memory cell according to an embodiment of the present invention. Fig. 12A is a schematic diagram showing a plurality of operating voltages of a switching gate circuit of a data bus as a function of temperature. Fig. 12B to 12D are schematic diagrams illustrating the temperature variation of the operating voltages according to the embodiment of fig. 11. Fig. 13 is a schematic circuit diagram of a switching gate circuit of a data bus according to an embodiment of the present invention. [ Symbolic description ] 100. 300, 500, 800 Semiconductor memory 110. 310, 510, 810 Pump circuit 111. 311, 511, 811 Charge pump 112. 312, 512, 812 Voltage comparator circuit 120. 320, 520, 820: Memory array 130. 330, 530, 830 Temperature sensor circuit 331. 531, 831 Temperature sensor 332 Voltage selector 333 Voltage dividing resistor 401. 402, 403, 404, 405 Logical code sequence code 900 Control circuit 901. 902, 903, 904, 905, 906, 907, 908, 909, 1101, 1301: Transistors 1100 Word line circuit 1121. 5311 C