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CN-115295041-B - PLM-14T anti-irradiation SRAM memory cell circuit

CN115295041BCN 115295041 BCN115295041 BCN 115295041BCN-115295041-B

Abstract

The invention relates to a PLM-14T anti-irradiation SRAM memory cell circuit. A PLM-14T anti-radiation SRAM memory cell circuit comprises ten NMOS transistors N1-N10 and four PMOS transistors P1-P4, P1 and P2 and P3 and P4 are in cross coupling, N1 and N2 correspond to P1 and P2 and serve as pull-down tubes, N3 and N4 correspond to P3 and P4 and serve as pull-down tubes, N5 and N6 form a feedback loop for adjusting a memory node, main memory nodes Q and QB are respectively connected with bit lines BL and BLB through N7 and N8, and redundant memory nodes S1 and S0 are respectively connected with the bit lines BL and BLB through N9 and N10. The storage node of the invention adopts the double pull-down loops to play a role of feedback regulation, thereby enhancing the anti-overturning capability of the circuit storage node. Meanwhile, the circuit uses four transmission transistors for reading and writing, so that the data writing speed and the writing noise margin of the unit are improved.

Inventors

  • ZHAO QIANG
  • MA YIFEI
  • WU XIULONG
  • PENG CHUNYU
  • LIN ZHITING
  • LU WENJUAN
  • CHEN JUNNING

Assignees

  • 安徽大学

Dates

Publication Date
20260512
Application Date
20220808

Claims (10)

  1. 1. A PLM-14T irradiation-resistant SRAM memory cell circuit, comprising: The N1-N10 and four PMOS transistors P1-P4, the sources of the transistors P1-P4 are electrically connected with VDD, the sources of the transistors N1-N6 are grounded, the transistors P1 and P2 and P3 and P4 are cross-coupled, the drain of the transistor N1 is electrically connected with the drain of P1, the gate of P2, the gate of N6 and the drain of N7, the gate of N1 is electrically connected with the drain of P3, the gate of P4, the drain of N3, the gate of N4, the drain of N6 and the drain of N10, the drain of the transistor N2 is electrically connected with the gate of P1, the drain of P2, the gate of N5 and the drain of N8, the gate of N2 is electrically connected with the gate of P3, the drain of P4, the gate of N3, the drain of N4 and the drain of N5 and the drain of N9; The memory device comprises bit lines BL, N7, N9, N8, N10, N7, N8, N9, N10, N7, N8, BL and BLB, S1 and S0, N9, N10, transistors N5 and N6, and a feedback loop for regulating the memory nodes, wherein the bit lines BL, N7, N9 and N9 are electrically connected with the source electrodes; Wherein Q is connected with BL through N7, QB is connected with BLB through N8, S1 is connected with BL through N9, S0 is connected with BLB through N10; N1 and N2 correspond to P1 and P2 as pull-down tubes, and N3 and N4 correspond to P3 and P4 as pull-down tubes.
  2. 2. The PLM-14T irradiation-resistant SRAM memory cell circuit of claim 1, wherein the transistors N1-N10 and P1-P4 have gate lengths of 65nm, the transistors N1-N4 have gate widths of 280nm, the transistors N5 and N6 have gate widths of 420nm, and the transistors N7-N10 and P1-P4 have gate widths of 140nm.
  3. 3. The PLM-14T irradiation resistant SRAM memory cell circuit of claim 1, wherein said storage nodes Q and QB are primary storage nodes and said storage nodes S1 and S0 are redundant storage nodes.
  4. 4. The PLM-14T irradiation resistant SRAM memory cell circuit of claim 1, wherein said transistors N7-N10 are pass transistors and are controlled by word lines WL.
  5. 5. The PLM-14T irradiation-resistant SRAM memory cell circuit of claim 4, wherein when the irradiation-resistant SRAM memory cell is in a hold phase, bit lines BL and BLB are precharged to a high level, word line WL is low, and an initial state is maintained inside the circuit.
  6. 6. The PLM-14T irradiation-resistant SRAM memory cell circuit of claim 4, wherein when the irradiation-resistant SRAM memory cell is in a read data phase, bit lines BL and BLB are precharged to a high level, word line WL is high level, and transistors N7-N10 are turned on.
  7. 7. The PLM-14T irradiation-resistant SRAM memory cell circuit of claim 6, wherein if the irradiation-resistant SRAM memory cell stores data of '0', the bit line BL is discharged through the discharge path 1: the transistors N9 and N5, the discharge path 2: the transistors N7 and N1, the discharge path 3: the transistors N9 and N4, the bit lines BL and BLB are caused to generate a voltage difference, and the data is read out through the sense amplifier.
  8. 8. The PLM-14T irradiation-resistant SRAM memory cell circuit of claim 6, wherein if the data stored in the irradiation-resistant SRAM memory cell is '1', the bit line BLB is discharged in the direction of transistors N8 and N2, N10 and N6 and N3 through a discharge path 1, and the transistors N10 and N3 generate a voltage difference, so that the bit lines BLB and BL generate a voltage difference, and the data is read out through a sense amplifier.
  9. 9. The PLM-14T irradiation-resistant SRAM memory cell circuit of claim 4, wherein the word line WL is high when the irradiation-resistant SRAM memory cell is in a data writing phase.
  10. 10. The PLM-14T irradiation-resistant SRAM memory cell circuit of claim 9, wherein if bit line BL is high, bit line BLB is low, then '1' is written to storage node Q and S1 through transistors N7 and N9, respectively, and if bit line BL is low, bit line BLB is high, then '1' is written to storage node QB and S1 through transistors N8 and N10, respectively.

Description

PLM-14T anti-irradiation SRAM memory cell circuit Technical Field The invention relates to the technical field of static random access memories, in particular to a unit circuit structure capable of improving the read-write speed of a memory unit and improving the single event upset resistance of the unit, namely a PLM-14T anti-irradiation SRAM memory unit circuit. Background When radiation particles pass through a Metal Oxide Semiconductor (MOS) device, their incident path generates a large number of electron-hole pairs, thereby losing energy. Due to the influence of the electric field and concentration gradient, radiation-induced carrier drift and diffusion are finally collected by the depletion region of the reverse biased junction, transient pulses are generated, and the probability of single event upset (SINGLE EVENT Upset, SEU) of the SRAM under the influence of the single event effect (SINGLE EVENT EFFECTS, SET) is higher and higher. Single Event Upset (SEUs) is a major reliability failure mechanism that can cause electronic system failure by temporarily changing the stored value. When a charged particle hits a sensitive node of an integrated circuit, induced charges along its path can be efficiently collected and accumulated by a drift process. The stored value in this sensitive node changes once the instantaneous voltage pulse generated by the accumulated charge exceeds the switching threshold of the circuit. SRAM circuits currently take on a large number of data exchange and data storage tasks in electronic systems, and the normal operation and operation of the entire electronic system is not supported by SRAM, which plays a vital role. So in order to reduce, even eliminate, the effect of radiation on the electronic system, radiation-resistant reinforcement of the SRAM is critical. Disclosure of Invention Based on this, there is a need for an improvement over conventional SRAMs in view of the problems associated with changing memory cell information due to anti-SEU, and the present invention provides a PLM-14T irradiation-resistant SRAM memory cell circuit. In order to achieve the above purpose, the present invention adopts the following technical scheme: A PLM-14T irradiation-resistant SRAM memory cell circuit, comprising: the grid electrode of the PMOS transistor P1, P1 is electrically connected with the drain electrode of P2, and the drain electrode of P1 is electrically connected with the drain electrode of N1; the grid electrode of the PMOS transistor P2, P2 is electrically connected with the drain electrode of the P1, and the drain electrode of the P2 is electrically connected with the grid electrode of the P1; the grid electrode of the PMOS transistor P3, P3 is electrically connected with the drain electrode of P4, and the drain electrode of P3 is electrically connected with the grid electrode of P4; The grid electrode of the PMOS transistor P4, P4 is electrically connected with the drain electrode of P3, and the drain electrode of P4 is electrically connected with the grid electrode of P3; the drains of the NMOS transistors N1 and N1 are electrically connected with the drain of the P1, and the grid of the N1 is electrically connected with the drain of the P3; The drain electrode of the NMOS transistor N2, the drain electrode of the N2 is electrically connected with the drain electrode of the P2, the grid electrode of the N2 is electrically connected with the drain electrode of the P4, and the source electrode of the N2 is electrically connected with the source electrode of the N1; The drains of the NMOS transistors N3 and N3 are electrically connected with the grid electrode of the P4 and the drain electrode of the P3, and the grid electrode of the N3 is electrically connected with the grid electrode of the P3 and the drain electrode of the P4; The drain electrode of the NMOS transistor N4, the drain electrode of the N4 is electrically connected with the grid electrode of the P3 and the drain electrode of the P4, the grid electrode of the N4 is electrically connected with the drain electrode of the N3, and the source electrode of the N4 is electrically connected with the source electrode of the N3; the drains of the NMOS transistors N5 and N5 are electrically connected with the grid electrode of the P3 and the drain electrode of the P4, and the grid electrode of the N5 is electrically connected with the drain electrode of the P2 and the drain electrode of the N2; The drains of the NMOS transistors N6 and N6 are electrically connected with the grid electrode of the P4 and the drain electrode of the P3, the grid electrode of the N6 is electrically connected with the drain electrode of the P1 and the drain electrode of the N1, and the source electrode of the N6 is electrically connected with the source electrode of the N5; The drains of the NMOS transistors N7 and N7 are electrically connected with the drain of the N1, the grid of the N7 is electrically connected with the word line WL, and the