CN-115295550-B - Semiconductor structure and forming method thereof

Abstract

A semiconductor structure and a forming method thereof comprise a substrate, a plurality of groups of groove structures, a plurality of capacitor structures and a plurality of bit lines, wherein the plurality of the groove structures are arranged in a third direction and penetrate through the plurality of active areas in the first direction, the third direction is perpendicular to the second direction, the first groove, the second groove and the third groove are arranged in parallel, the third direction forms an acute angle with the first direction, the pseudo gate structures are arranged in the first groove, the first word gate structures are arranged in the second groove, the second word gate structures are arranged in the third groove, the second isolation layer is arranged between the first word gate structures and the second word gate structures, the second isolation layer penetrates through the plurality of active areas in the first direction, the capacitor structures are arranged on the first surface of the substrate, and the bit lines are arranged on the second surface of the substrate in parallel to the third direction and in the first direction. The formation process of the semiconductor structure is simplified.

Inventors

• HUA WENYU
• DING XIAO

Assignees

• 芯盟科技有限公司

Dates

Publication Date

20260512

Application Date

20220729

Claims (20)

1. 1. A semiconductor structure, comprising: The substrate is provided with a first surface and a second surface which are opposite, the substrate comprises a plurality of active areas and a first isolation layer, the active areas are arranged along a first direction, the first isolation layer is positioned between the adjacent active areas, the projection graph of each active area on the first surface or the second surface is in a strip shape, the strip shape is provided with two long sides which are parallel to each other, and the long side direction is parallel to a second direction; the plurality of groups of groove structures are positioned in the substrate, extend from the first surface to the second surface, are distributed along a third direction, penetrate through the plurality of active areas along the first direction and are perpendicular to the first direction, and comprise a first groove, a second groove and a third groove which are arranged in parallel along the third direction, wherein the first groove, the second groove and the third groove are separated from each other, and an acute angle is formed between the third direction and the second direction; A dummy gate structure located within the first recess; A first word line gate structure located in the second recess; the second word line grating electrode structure is positioned in the third groove, and the distance between the adjacent first word line grating electrode structure and the second word line grating electrode structure is smaller than the distance between the adjacent pseudo gate electrode structure and the first word line grating electrode structure; The second isolation layer is positioned between the first word line grating electrode structure and the second word line grating electrode structure, the second isolation layer penetrates through the active areas along the first direction, and the first word line grating electrode structure and the second word line grating electrode structure are respectively adjacent to and contacted with the second isolation layer; The capacitor structures are positioned on the first surface of the substrate, are electrically connected with the corresponding active areas, and are positioned on the active areas on two sides of the pseudo gate structure; And a plurality of bit lines on the second surface of the substrate, wherein the bit lines are parallel to the third direction and are distributed along the first direction, and each bit line is electrically connected with the plurality of active areas.
2. 2. The semiconductor structure of claim 1, further comprising a first source drain doped region within the active region of the first side of the substrate, wherein the capacitive structure is electrically connected to the first source drain doped region, and wherein a projection of the capacitive structure onto the first side of the substrate coincides with at least a portion of the first source drain doped region.
3. 3. The semiconductor structure of claim 2, wherein the second isolation layer extends from the first side to the second side of the substrate, and wherein the second isolation layer has a depth greater than a depth of the first and second word line gate structures.
4. 4. The semiconductor structure of claim 3, further comprising a bitline plug located between the active region and the bitline, the bitline plug being located on the active region between the first and second wordline gate structures.
5. 5. The semiconductor structure of claim 2, wherein the second isolation layer extends from the second side of the substrate toward the first side, and wherein a spacing of the second isolation layer from the first side of the substrate is less than a spacing of the first and second word line gate structures from the first side of the substrate.
6. 6. The semiconductor structure of claim 5, wherein the capacitor structure is located on the active region on both sides of the dummy gate structure.
7. 7. The semiconductor structure of claim 1, wherein the substrate second side exposes the first isolation layer bottom surface.
8. 8. The semiconductor structure of claim 7, further comprising a second source drain doped region located within the active region on the second side of the substrate, the bit line being electrically connected to the second source drain doped region.
9. 9. The semiconductor structure of claim 8, wherein a thickness of the second source drain doped region is greater than a thickness of the first isolation layer at a bottom of the first word line gate structure, at a bottom of the second word line gate structure.
10. 10. The semiconductor structure of claim 2, wherein a top surface of the dummy gate structure, the first word line gate structure, the second word line gate structure is lower than the substrate first face surface.
11. 11. The semiconductor structure of claim 10, wherein a bottom surface of the first source drain doped region is lower than a top surface of the dummy gate structure, first word line gate structure, second word line gate structure.
12. 12. The semiconductor structure of claim 1, wherein a bottom plane of the dummy gate structure, the first word line gate structure, the second word line gate structure is higher than a bottom plane of the first isolation layer.
13. 13. The semiconductor structure of claim 1, wherein the material of the dummy gate structure, the first word line gate structure, and the second word line gate structure comprises polysilicon.
14. 14. The semiconductor structure of claim 1, wherein the dummy gate structure, the first word line gate structure, and the second word line gate structure comprise a composite structure comprising a first gate layer and a second gate layer on the first gate layer, wherein a material of the first gate layer comprises polysilicon and a material of the second gate layer comprises tungsten metal.
15. 15. The semiconductor structure of claim 1, wherein the third direction and the second direction have an included angle ranging from 0 degrees to 45 degrees.
16. 16. A method of forming a semiconductor structure, comprising: providing a substrate, wherein the substrate is provided with a first surface and a second surface which are opposite, the substrate comprises a plurality of active areas and a first isolation layer, the active areas are arranged along a first direction, the first isolation layer is positioned between adjacent active areas, the projection pattern of each active area on the first surface or the second surface is in a strip shape, the strip shape is provided with two long sides which are parallel to each other, and the long side direction is parallel to a second direction; Forming a plurality of groups of groove structures in the substrate, wherein the groove structures extend from the first surface to the second surface, the groove structures are distributed along a third direction, the groove structures penetrate through the active areas along the first direction, the third direction is perpendicular to the first direction, the groove structures comprise a first groove, a second groove and a third groove which are arranged in parallel along the third direction, the first groove, the second groove and the third groove are separated from each other, and the third direction forms an acute angle with the second direction; forming a dummy gate structure in the first groove; forming a first word line gate structure in the second groove; forming a second word line gate structure in the third groove, wherein the distance between the adjacent first word line gate structure and the second word line gate structure is smaller than the distance between the adjacent dummy gate structure and the first word line gate structure; Forming a second isolation layer between the first word line gate structure and the second word line gate structure, wherein the second isolation layer penetrates through a plurality of active areas along a first direction, and the first word line gate structure and the second word line gate structure are respectively adjacent to and contacted with the second isolation layer; Forming a plurality of capacitor structures on the first surface of the substrate, wherein the capacitor structures are electrically connected with the corresponding active areas, and the capacitor structures are positioned on the active areas at two sides of the pseudo gate structure; and forming a plurality of bit lines on the second surface of the substrate, wherein the bit lines are parallel to the third direction and are distributed along the first direction, and each bit line is electrically connected with the plurality of active areas.
17. 17. The method of forming a semiconductor structure as recited in claim 16, further comprising forming a first source drain doped region in an active region of the first side of the substrate prior to forming the plurality of capacitor structures on the first side of the substrate, wherein the capacitor structures are electrically connected to the first source drain doped region, and wherein a projection of the capacitor structures onto the first side of the substrate coincides with at least a portion of the first source drain doped region.
18. 18. The method of claim 17, wherein the second spacer extends from the first side to the second side of the substrate, and wherein the second spacer has a depth greater than a depth of the first and second word line gate structures.
19. 19. The method of forming a semiconductor structure as claimed in claim 18, wherein the forming of the second isolation layer includes forming a fourth recess in the substrate after forming the dummy gate structure, the first word line gate structure and the second word line gate structure, the fourth recess extending from the first side of the substrate toward the second side of the substrate, the fourth recess extending through the plurality of active regions in the first direction, the fourth recess exposing sidewall surfaces of the first word line gate structure and the second word line gate structure, and forming a second isolation layer in the fourth recess.
20. 20. The method of forming a semiconductor structure as recited in claim 18 further comprising forming a bitline plug between said active region and a bitline, said bitline plug being located on the active region between the first and second wordline gate structures.

Description

Semiconductor structure and forming method thereof Technical Field The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same. Background With rapid development of technology nowadays, semiconductor memories are widely used in electronic devices. Dynamic random access memory (dynamic random access memory, DRAM) is one of the volatile memories, which is the most commonly utilized solution for applications storing large amounts of data. The basic memory cell of the dynamic random access memory is composed of one memory transistor and one memory capacitor, and the memory array is composed of a plurality of memory cells. The storage capacitor is used for storing charge representing stored information, the storage transistor is a switch for controlling charge inflow and discharge of the storage capacitor, and the storage transistor is also connected with an internal circuit in storage and receives a control signal of the internal circuit. Wherein an active region, a drain region, and a gate electrode are formed in the memory transistor, the gate electrode is used for controlling current flow between the source region and the drain region, and is connected to the word line, the drain region is used for forming a bit line contact region, and is connected to the bit line source region for forming a storage node contact region, so as to be connected to the storage capacitor. With the continued development of integrated circuit fabrication technology, further increases in device density of memory chips are needed to obtain greater amounts of data storage. In summary, the existing dynamic random access memory needs to be improved. Disclosure of Invention The invention solves the technical problem of providing a semiconductor structure and a forming method thereof, and improves the performance of a memory. In order to solve the technical problems, the technical scheme of the invention provides a semiconductor structure, which comprises a substrate, a first isolation layer and a second isolation layer, wherein the substrate is provided with a first surface and a second surface which are opposite, the substrate comprises a plurality of active areas and the first isolation layer which are arranged along a first direction, the first isolation layer is positioned between the adjacent active areas, the projection graph of each active area on the first surface or the second surface is in a strip shape, and the strip shape is provided with a long side, and the direction of the long side is parallel to the second direction; the substrate comprises a plurality of groups of groove structures, a plurality of active regions, a plurality of first grooves, a plurality of second grooves and a plurality of first grooves, wherein the plurality of groove structures are arranged in a first direction, extend from a first face to a second face, penetrate through the plurality of active regions in the first direction, are perpendicular to the first direction, and comprise a first groove, a second groove and a third groove which are arranged in parallel in the third direction, the first groove, the second groove and the third groove are separated from each other, and the third direction forms an acute angle with the second direction; the device comprises a first groove, a dummy gate structure in the first groove, a first word line gate structure in the second groove, a second word line gate structure in the third groove, a second isolation layer between the first word line gate structure and the second word line gate structure, the second isolation layer penetrating through a plurality of active areas along a first direction, the first word line gate structure and the second word line gate structure are adjacent to the second isolation layer respectively, a plurality of capacitor structures on a first surface of a substrate, the capacitor structures are electrically connected with corresponding active layers, a plurality of bit lines on a second surface of the substrate, the bit lines are parallel to the third direction and are distributed along the first direction, each bit line is electrically connected with a plurality of active areas. Optionally, the semiconductor device further comprises a first source-drain doped region positioned in the active region of the first surface of the substrate, wherein the capacitor structure is electrically connected with the first source-drain doped region, and the projection of the capacitor structure on the first surface of the substrate is at least overlapped with part of the first source-drain doped region. Optionally, the second isolation layer extends from the first surface to the second surface of the substrate, and the depth of the second isolation layer is greater than the depths of the first word line gate structure and the second word line gate structure. Optionally, a bit line plug between the active regio