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CN-115308988-B - Method of manufacturing semiconductor device and pattern forming method of manufacturing semiconductor device

CN115308988BCN 115308988 BCN115308988 BCN 115308988BCN-115308988-B

Abstract

The application discloses a method of manufacturing a semiconductor device and a pattern forming method of manufacturing a semiconductor device. In a pattern forming method for semiconductor device manufacturing, an original pattern for manufacturing a photomask is obtained, a modified original pattern is obtained by performing optical proximity correction on the original pattern, a sub-resolution assist feature (SRAF) seed pattern is obtained with respect to the modified original pattern, the SRAF seed pattern indicating a position where image quality is improved by the SRAF pattern, the SRAF pattern is placed around the original pattern, the SRAF pattern and the modified original pattern are output as mask data, and the photomask is manufactured using the mask data.

Inventors

  • YAMAZOE KENJI
  • WU BINGJIE
  • WU HAITAO
  • HE LIJIAN

Assignees

  • 台湾积体电路制造股份有限公司

Dates

Publication Date
20260512
Application Date
20220527
Priority Date
20220331

Claims (4)

  1. 1. A pattern forming method for semiconductor device fabrication, comprising: Acquiring an original pattern for manufacturing a photomask; obtaining a modified original pattern by performing optical proximity correction on the original pattern; Obtaining a sub-resolution assist feature seed map relative to the modified original pattern, the sub-resolution assist feature seed map indicating locations at which image quality is improved by sub-resolution assist feature patterns, wherein obtaining the sub-resolution assist feature seed map comprises finding locations at which placement unit patterns can improve image quality of the modified original pattern, and wherein the image quality comprises image slopes of edges of the modified original pattern; Placing a pattern of sub-resolution assist features around the original pattern; performing a design rule check operation on the sub-resolution assist feature pattern and the modified original pattern; outputting the sub-resolution assist feature pattern and the modified original pattern as mask data, and The photomask is fabricated using the mask data.
  2. 2. The pattern forming method as claimed in claim 1, further comprising performing another optical proximity correction on the sub-resolution assist feature pattern and the modified original pattern, Wherein the mask data includes the sub-resolution assist feature pattern and the modified original pattern on which the further optical proximity correction is performed.
  3. 3. The pattern forming method according to claim 1, wherein one or more of the sub-resolution assist feature pattern or the modified original pattern is modified after the design rule checking operation.
  4. 4. The pattern forming method according to claim 1, wherein the unit pattern is a square having a size of 2nm to 40 nm.

Description

Method of manufacturing semiconductor device and pattern forming method of manufacturing semiconductor device Technical Field The present disclosure relates to a method of manufacturing a semiconductor device and a pattern forming method of manufacturing a semiconductor device. Background The electronics industry has experienced an ever-increasing demand for smaller and faster electronic devices to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low cost, high performance and low power integrated circuits (INTEGRATED CIRCUIT, ICs). To date, these goals have been largely achieved by shrinking semiconductor IC dimensions (e.g., minimum feature sizes) and thereby improving production efficiency and reducing associated costs. However, this shrinkage also increases the complexity of the semiconductor manufacturing process. Accordingly, similar advances in semiconductor manufacturing processes and techniques are needed to realize continued advances in semiconductor ICs and devices. As just one example, shrinking IC sizes has been achieved by expanding the available resolution of a given lithographic generation using one or more resolution enhancement techniques (resolution enhancement technology, RET) (e.g., phase shift mask (PHASE SHIFT MASK, PSM), off-axis illumination (off-axis illumination, OAI), optical proximity correction (optical proximity correction, OPC), and inserting sub-resolution assist features (sub-resolution assist feature, SRAF) in the design layout. Several SRAF insertion or placement techniques have been proposed. Some of which are rule-based, have relatively short turn-around times, but accuracy is far from ideal. Some of these use multiple mask optimization iterations to achieve excellent accuracy, but require a long time for each SRAF insertion exercise. Thus, the prior art has not proved to be entirely satisfactory in all respects. Disclosure of Invention According to a first aspect of the present disclosure, there is provided a pattern forming method for semiconductor device fabrication, including obtaining an original pattern for fabricating a photomask, obtaining a modified original pattern by performing optical proximity correction on the original pattern, obtaining sub-resolution assist feature (SRAF) seed patterns relative to the modified original pattern, the SRAF seed patterns indicating positions where image quality is improved by the SRAF pattern, placing the SRAF pattern around the original pattern, outputting the SRAF pattern and the modified original pattern as mask data, and fabricating the photomask using the mask data. According to a second aspect of the present disclosure, there is provided a pattern forming method for semiconductor device fabrication, including obtaining an original pattern for fabricating a photomask, calculating a sub-resolution assist feature (SRAF) seed map to find candidate locations where placing an SRAF can improve an image slope of an edge of an optical image of the original pattern, placing an SRAF pattern at one or more of the candidate locations, outputting the SRAF pattern and the original pattern as mask data, fabricating the photomask using the mask data, and forming a resist pattern by photolithography using the photomask. According to a third aspect of the present disclosure there is provided an apparatus for manufacturing a photomask comprising a processor and a non-transitory computer readable storage medium storing a program, wherein the program when executed by the processor causes the processor to perform the operations of obtaining an original pattern for manufacturing a photomask, calculating a sub-resolution assist feature (SRAF) seed map to find candidate locations where placing an SRAF can improve an image slope of an edge of an optical image of the original pattern, placing an SRAF pattern at one or more of the candidate locations, and outputting the SRAF pattern and the original pattern as mask data. Drawings Aspects of the disclosure may be best understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various features are not drawn to scale according to industry standard practices. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Fig. 1 is a schematic diagram of components of an exposure tool according to aspects of the present disclosure. Fig. 2 is a flow chart of an embodiment of a method of manufacturing a photomask according to aspects of the present disclosure. Fig. 3 is a schematic diagram of components of an exposure tool according to aspects of the present disclosure. Fig. 4A and 4B illustrate examples of mask patterns according to various embodiments of the present disclosure. Fig. 5A, 5B, 5C, and 5D illustrate schematic diagrams of obtaining SRAF seed patterns a