CN-115314030-B - Single-channel wide dynamic range single fast pulse signal acquisition system

CN115314030BCN 115314030 BCN115314030 BCN 115314030BCN-115314030-B

Abstract

The invention relates to a high-speed signal acquisition system, in particular to a single-channel wide-dynamic-range single fast pulse signal acquisition system, which solves the technical problem of large dynamic range acquisition of single fast pulse P1. The invention provides a single-channel wide dynamic range single fast pulse signal acquisition system which comprises a composite pulse string forming circuit S1, a data acquisition unit S2 and an acquisition and restoration unit S3, wherein the composite pulse string forming circuit S1 comprises a power dividing circuit U1, N attenuation circuits U2, N analog delay circuits U3 and a composite circuit U4, N is an integer larger than 1, an input end of the composite pulse string forming circuit S1 receives fast pulses P1, the input fast pulses P1 are branched and then delayed respectively, and finally, the single fast pulse string P1 is compounded into a pulse string P2, multiple sampling is realized on single fast pulse P1 signals in a short time by utilizing a single recording channel, and meanwhile, the large dynamic range acquisition of the single fast pulse P1 signals can be realized by configuring attenuation parameters of different branches.

Inventors

LUO TONGDING
ZHANG YANXIA
LI BINKANG
ZHAO QIAN
WANG JING
Lv Zongjing
TIAN GENG
RUAN LINBO
LI HAITAO
CHEN YANLI

Assignees

西北核技术研究所

Dates

Publication Date: 20260505
Application Date: 20220720

Claims (10)

1. The single-channel wide dynamic range single fast pulse signal acquisition system is characterized by comprising a composite pulse train forming circuit S1, a data acquisition unit S2 and an acquisition and recovery unit S3; The composite pulse string forming circuit S1 comprises a power dividing circuit U1, N attenuating circuits U2, N analog delay circuits U3 and a composite circuit U4, wherein N is an integer greater than 1; The input end of the power dividing circuit U1 is used for receiving an input fast pulse P1, dividing the input fast pulse P1 into N paths of pulse signals and respectively inputting the N paths of pulse signals into N attenuation circuits U2; the N attenuation circuits U2 respectively carry out gain adjustment on N paths of pulse signals to form N paths of pulses with different gains, and the N paths of pulses with different gains are respectively input into the corresponding N analog delay circuits U3; N analog delay circuits U3 respectively add N signal delay times T D1 、…、T DN into corresponding N pulses with different gains to generate N phase separation pulses which are respectively input into the input end of a composite circuit U4, wherein the composite circuit U4 synthesizes the N phase separation pulses into a pulse string P2 and inputs the pulse string P2 into the input end of a data acquisition unit S2; the data acquisition unit S2 is used for digitizing the waveform of the pulse string P2 to obtain waveform data, and the data acquisition unit S2 and the acquisition and restoration unit S3 are in communication connection with each other; The acquisition and reduction unit S3 is configured to extract sampling results of the multiple fast pulses P1 from the digitized waveform data, and obtain sampling waveforms of different ranges according to the calibrated vertical sensitivity and delay time, so as to achieve large dynamic range acquisition of the single input fast pulse P1.
2. The system for acquiring the single-channel wide dynamic range single fast pulse signal according to claim 1, wherein the power dividing circuit U1 is a discrete resistor circuit, the attenuation circuit U2 is an integrated attenuator or a discrete resistor, the analog delay circuit U3 is an analog delay line device, and the composite circuit U4 is a composite pulse train shaper based on an adder principle.
3. The single channel wide dynamic range single fast pulse signal acquisition system according to claim 1 or 2, wherein said power dividing circuit U1 comprises a resistor R1, a resistor R 01 , a resistor R 02 , a resistor R 0N ; One end of the resistor R1 is connected with the fast pulse P1, and the other end of the resistor R1 is respectively connected with one end of the resistor R 01 , one end of the resistor R 02 , and one end of the resistor R 0N ; The other ends of the resistor R 01 , the resistor R 02 and the resistor R 0N are respectively connected with the input ends of the N attenuation circuits U2.
4. The single channel wide dynamic range single fast pulse signal acquisition system according to claim 3, wherein said attenuation circuit U2 comprises a resistor R5, a resistor R6 and a resistor R7; One end of the resistor R7 is connected with one end of the resistor R5, and the other end of the resistor R7 is connected with one end of the resistor R6, wherein the other end of the resistor R5 is grounded, and the other end of the resistor R6 is grounded; One end of the resistor R7 of the N attenuation circuits U2 connected with the resistor R5 is respectively connected with the other ends of the resistor R 01 , the resistor R 02 and the resistor R 0N ; And one ends of the resistors R7 and R6 of the N attenuation circuits U2 are respectively connected with the input ends of the N analog delay circuits U3.
5. The single channel wide dynamic range single fast pulse signal acquisition system according to claim 4, wherein said analog delay circuit U3 comprises a resistor R, a resistor Rin, a resistor Rout and an analog delay line device; One end of the resistor Rin is connected with one end of the resistor R, the other end of the resistor Rin is connected with the input end of the analog delay line device, and the output end of the analog delay line device is connected with one end of the resistor Rout; the other end of the resistor R is grounded, and the other end of the resistor Rout is grounded; One end of the resistor Rin connected with the resistor R is connected with one end of the resistor R7 connected with the resistor R6 of the corresponding attenuation circuit U2; The output ends of the analog delay line devices of the N analog delay circuits U3 are respectively connected with the input ends of the composite circuit U4.
6. The single channel wide dynamic range single fast pulse signal acquisition system according to claim 5, wherein said composite circuit U4 comprises resistor R C1 , resistor R C2 , resistor R CN ; One end of the resistor R C1 , one end of the resistor R C2 and one end of the resistor R CN are respectively connected with the output end of the corresponding analog delay device; The other end of the resistor R C1 , the other end of the resistor R C2 , the other end of the resistor R CN are connected, and are used as an output end of the composite circuit U4 and are connected with an input end of the data acquisition unit S2.
7. The system of claim 6, wherein the data acquisition unit S2 comprises a radio frequency driving unit, an analog-to-digital converter, a processor unit, a clock synchronization unit, a storage unit, a trigger unit, an interface unit and a bias unit; The output end of the radio frequency driving unit is connected with the input end of an analog-to-digital converter, and the output end of the analog-to-digital converter is connected with the input end of the processor unit; the output end of the processor unit is respectively connected with the control input ends of the radio frequency driving unit and the analog-to-digital converter; The output end of the clock synchronization unit is respectively connected with the analog-to-digital converter, the processor unit and the storage unit and is used for providing clock signals; The input end of the trigger unit is used for receiving an external trigger unit signal Trig, and the output end of the trigger unit signal Trig is connected with the input end of the trigger unit of the processor unit; The output end of the bias unit is connected with the input end of the radio frequency driving unit; the interface unit is in communication connection with the acquisition and reduction unit S3.
8. The single channel wide dynamic range single fast pulse signal acquisition system according to claim 7, wherein said composite pulse train shaping circuit S1 further comprises a clipping protection circuit U5; The limiting protection circuit U5 comprises a diode Q1 and a diode Q2, wherein the anode of the diode Q1 is connected with the cathode of the diode Q2 and is connected with the output end of the composite circuit U4; the negative electrode of the diode Q1 is connected with a positive power supply V+, and the positive electrode of the diode Q2 is connected with a negative power supply V-.
9. The system for collecting single fast pulse signals with wide dynamic range of single channel as set forth in claim 8, wherein N has a value of 3.
10. The single-channel wide dynamic range single fast pulse signal acquisition system according to claim 9, wherein the impedance of the power dividing circuit U1 is 50Ω, R1=24.9Ω; said r5=r 6=61.1Ω of the total number of the pieces, r7=24.7Ω; The resistor R is 50Ω, rin=rout=z line =50Ω, where Z line is the impedance of the analog delay; The R C1 =R C2 =R C3 ,(R line1 +R C1 )//(R line2 +R C2 )//(R line3 +R C3 )=50Ω,, wherein R line1 、R line2 、R line3 each represent the output impedance of the corresponding analog delay circuit U3.

Description

Single-channel wide dynamic range single fast pulse signal acquisition system Technical Field The invention relates to a high-speed signal acquisition system, in particular to a single-channel wide dynamic range single fast pulse signal acquisition system. Background The rapid pulse signal measurement has wide application in scientific experimental researches such as high-energy physics, radiation detection, detonation experiments and the like. The occurrence process of the physical experiments is extremely short, the physical detection signals have the characteristic of transient, and the time width is usually in the order of nanoseconds to microseconds. The most important is that its amplitude has the characteristics of uncertainty and large span, and the amplitude range may cover several millivolts to several hundred volts. In addition, the signal has the characteristics of non-periodicity and single unrepeatable, and great challenges are brought to accurate acquisition of the signal. At present, a multi-range coverage method is often adopted for the acquisition of the single fast pulse signal, and the principle is that a power divider is utilized to divide the signal into multiple paths, then a plurality of oscilloscopes or data acquisition instrument channels are utilized to acquire the signal in a range lap joint mode, and the channels are respectively covered with different amplitude ranges of the fast pulse signal by setting different gains. The acquisition method can acquire the fast pulse signals, but has the problem of inconsistency caused by the differences of synchronous triggering, biasing, conditioning circuits, analog-to-digital converters and the like among different channels. Disclosure of Invention The invention aims to provide a single-channel wide dynamic range single fast pulse signal acquisition system, which aims at the technical problem of inconsistency caused by differences of a synchronous trigger unit, a bias unit, a conditioning circuit, an analog-to-digital converter and the like among different channels in a method for acquiring common multi-range coverage of a single fast pulse in a large dynamic range, and utilizes a single recording channel to realize multiple sampling of a single fast pulse P1 signal in a short time, and meanwhile, can realize large dynamic range acquisition of the single fast pulse P1 signal by configuring attenuation parameters of different branches. In order to solve the technical problems, the invention adopts the following technical scheme: The single-channel wide dynamic range single fast pulse signal acquisition system is characterized by comprising a composite pulse train forming circuit S1, a data acquisition unit S2 and an acquisition and recovery unit S3; The composite pulse train forming circuit S1 comprises a power dividing circuit U1, N attenuating circuits U2, N analog delay circuits U3 and a composite circuit U4, wherein N is an integer greater than 1; The input end of the power dividing circuit U1 is used for receiving an input fast pulse P1, dividing the input fast pulse P1 into N paths of pulse signals and respectively inputting the N paths of pulse signals into N attenuation circuits U2; The N attenuation circuits U2 respectively carry out gain adjustment on N paths of pulse signals to form N paths of pulses with different gains, and the N paths of pulses are respectively input into the corresponding N analog delay circuits U3; n analog delay circuits U3 respectively add N signal delay times T D1、…、TDN into N pulses with different gains, generate N phase separation pulses and respectively input the N phase separation pulses into the input end of a composite circuit U4; The composite circuit U4 synthesizes N phase separation pulses into a pulse string P2 and inputs the pulse string P2 to the input end of the data acquisition unit S2; The data acquisition unit S2 is used for digitizing the waveform of the pulse string P2 to obtain waveform data, and the data acquisition unit S2 and the acquisition and restoration unit S3 are in communication connection with each other; The acquisition and reduction unit S3 is configured to extract sampling results of the multiple fast pulses P1 from the digitized waveform data, and obtain sampling waveforms of different ranges according to the calibrated vertical sensitivity and delay time, so as to achieve large dynamic range acquisition of the single input fast pulse P1. Further, the power dividing circuit U1 is a discrete resistor circuit, the attenuation circuit U2 adopts an integrated attenuator or a discrete resistor, the analog delay circuit U3 is an analog delay line device, and the composite circuit U4 is a composite pulse string shaper based on the adder principle. Further, the power dividing circuit U1 includes a resistor R1, a resistor R 01, a resistor R 02, a resistor R 0N; One end of the resistor R1 is connected with the fast pulse P1, and the other end of the resistor R1 is respectively con