CN-115315781-B - Method for manufacturing bonded wafer and bonded wafer

Abstract

The present invention provides a method for manufacturing a bonded wafer by bonding a compound semiconductor wafer obtained by epitaxially growing a compound semiconductor on a growth substrate to a bonded wafer, wherein the area of the bonding surface of the bonded wafer is made larger than the area of the bonding surface of the compound semiconductor wafer, and the growth substrate is removed after bonding the bonded wafer to the compound semiconductor wafer. Thus, a method for manufacturing a bonded wafer can be provided which can suppress the occurrence of cracks.

Inventors

• ISHIZAKI JUNYA
• FURUYA SHOGO

Assignees

• 信越半导体株式会社

Dates

Publication Date

20260512

Application Date

20210308

Priority Date

20200325

Claims (6)

1. 1. A method for manufacturing a bonded wafer by bonding a compound semiconductor wafer obtained by epitaxially growing a compound semiconductor on a growth substrate to a bonded wafer, characterized by comprising, The area of the bonding surface of the bonded wafer is made larger than the area of the bonding surface of the compound semiconductor wafer, The bonding between the bonded wafer and the compound semiconductor wafer is any one of direct bonding without any substance, metal bonding via metal, and bonding via polymer, The compound semiconductor wafer is arranged such that the center of the compound semiconductor wafer is offset from the center of the bonded wafer by 1 to 5mm, The compound semiconductor side of the compound semiconductor wafer subjected to epitaxial growth is used as a bonding surface to be bonded with a bonded wafer, and then the growth substrate is removed, The total thickness of the compound semiconductor wafer from which the growth substrate is removed is set to 15 μm or less.
2. 2. The method for manufacturing a bonded wafer according to claim 1, The metal comprises one or more of Au, ag, al, in, ga.
3. 3. The method for manufacturing a bonded wafer according to claim 1, The polymer is resin.
4. 4. The method for manufacturing a bonded wafer according to claim 3, The resin is benzocyclobutene, polyimide or glass using TEOS.
5. 5. The method for manufacturing a bonded wafer according to any one of claims 1 to 4, The bonded wafer is set to silicon, sapphire or quartz.
6. 6. A bonded wafer formed by bonding a bonded wafer having an area larger than the area of the bonding surface of a compound semiconductor wafer to the compound semiconductor wafer, It is characterized in that the method comprises the steps of, The bonded wafer according to the method for manufacturing a bonded wafer of any one of claims 1 to 5, The bonding between the bonded wafer and the compound semiconductor wafer is any one of direct bonding without any substance, metal bonding via metal, and bonding via polymer, The center of the compound semiconductor wafer is deviated from the center of the bonded wafer by 1 to 5mm, The total thickness of the compound semiconductor wafer is 15 μm or less.

Description

Method for manufacturing bonded wafer and bonded wafer Technical Field The present invention relates to a method for manufacturing a bonded wafer and a bonded wafer. Background Epitaxial wafers (EPW) for various compound semiconductor elements can be realized by using GaAs substrates or InP substrates. The largest diameter GaAs substrate was a 6 inch (150 mm) substrate and the largest diameter InP substrate was a4 inch (100 mm) substrate. Although it is necessary to form electrodes and implement a step of forming elements after the production of EPW, a production apparatus having a diameter of 8 inches (200 mm) or more is currently mainly used, and it is difficult to purchase a new apparatus having a diameter of 6 inches or less. Accordingly, various methods have been proposed for performing a device process on a small-diameter wafer using a large-diameter device. One of the methods is a method in which a Template (Template) is prepared by cutting a small-diameter groove in a large-diameter wafer, and a compound semiconductor wafer is mounted on the Template to perform a process. This method is simple and inexpensive, but has a problem that physical adhesion between the template and the wafer is not possible. In addition, in the photolithography step, a step of heating the wafer by a heating plate is required before and after the photoresist is exposed, but if the adhesion to the template is low, the thermal resistance between the template and the wafer becomes large, and there is a problem that the photolithography condition cannot be stabilized. In order to solve the above problem, the template wafer needs to be closely adhered to EPW. Patent document 1 discloses a method of bonding a template wafer to EPW with a polyimide temporary fixing material to perform a process. This method is an excellent method in terms of adhesion to the template, but it requires peeling from the template after device fabrication, and in principle, it requires an additional removal step because residues are generated on the peeled surface. Since polyimide cannot be sufficiently removed by thermal decomposition or an organic solvent, oxygen plasma ashing needs to be applied, and there is a problem in that the surface of the compound wafer is oxidized in the removal process. In addition, compound EPW has a heteroepitaxial structure. In heterogeneous epitaxy, growth is performed at a growth temperature such that the lattice constants are substantially uniform, and warpage due to a difference in thermal expansion coefficient occurs when the temperature is lowered to room temperature. That is, internal stress is generated in the compound semiconductor epitaxial layer at room temperature. The internal stress varies continuously with temperature. The higher the temperature at the time of joining, the greater the difference in internal stress at the time of lowering to room temperature. When the bonded wafer serving as a template and EPW are made of different materials, stress due to a difference in thermal expansion coefficient is applied to the compound semiconductor wafer in principle. In the case of a substrate having a thermal expansion coefficient of less than EPW, when the temperature at the time of bonding is lowered to room temperature, a tensile stress is applied to the EPW substrate. The greater the tensile stress, the more likely the substrate will fracture. When the template substrate is silicon, since the thermal expansion coefficient thereof is smaller than that of the compound semiconductor, the compound semiconductor EPW bonded by heating is subjected to tensile stress after the temperature thereof is lowered to room temperature. When bonding to wafers of different diameters and at temperatures of 200 ℃ or higher, a plurality of cracks are often generated in the compound semiconductor, and the compound semiconductor EPW is damaged. This is a problem caused by internal stress caused by a difference in thermal expansion coefficient, and joining in a conventional manner alone cannot solve the problem. Prior art literature Patent literature Patent document 1 Japanese patent No. 6213977 Disclosure of Invention Technical problem to be solved by the invention The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a method for manufacturing a bonded wafer, which can suppress occurrence of cracks in an epitaxial layer when a compound semiconductor epitaxial wafer having a small diameter or a small size is bonded to a wafer to be bonded to manufacture a substrate capable of device programming. Technical means for solving the technical problems In order to achieve the above object, the present invention provides a method for manufacturing a bonded wafer by bonding a compound semiconductor wafer obtained by epitaxially growing a compound semiconductor on a growth substrate to a bonded wafer, characterized in that the area of the bonding surface of the bonde