CN-115332178-B - Method for manufacturing semiconductor memory device

Abstract

The invention provides a method for manufacturing a semiconductor memory device, which comprises providing a substrate; A method for forming a semiconductor device includes forming a plurality of first grooves along a first direction on a substrate, depositing a conductive material in the plurality of first grooves to form a word line structure, forming a word line cap in the plurality of first grooves, forming a plurality of second grooves along a second direction on the substrate, the first direction intersecting the second direction, and forming an active region in the second grooves. The invention can improve the manufacturing efficiency of the semiconductor memory device.

Inventors

• Lv Yinzhun
• YANG TAO
• LI JUNFENG
• WANG WENWU

Assignees

• 中国科学院微电子研究所
• 中国科学院微电子研究所
• 真芯(北京)半导体有限责任公司
• 真芯(北京)半导体有限责任公司

Dates

Publication Date

20260421

Application Date

20210510

Priority Date

20210510

Claims (10)

1. 1. A method of manufacturing a semiconductor memory device, comprising: Providing a substrate; Forming a plurality of first grooves along a first direction on an upper surface of the substrate; depositing conductive material in the plurality of first grooves to form a word line structure; forming word line covers in the first grooves; forming a plurality of second grooves on the upper surface of the substrate along a second direction, wherein the first direction intersects with the second direction; An active region is formed within the second recess.
2. 2. The method of manufacturing a semiconductor memory device according to claim 1, wherein before the step of depositing the conductive material in the plurality of first grooves, the method further comprises: And forming a gate dielectric layer on the side walls and the bottom surfaces of the plurality of first grooves.
3. 3. The method of manufacturing a semiconductor memory device according to claim 2, wherein the material of the gate dielectric layer comprises a silicon oxide layer, a thermal oxide layer, or a high-k dielectric layer.
4. 4. The method of manufacturing a semiconductor memory device according to claim 1, wherein a width of the word line cap in a third direction is not smaller than a width of the word line structure in the third direction, the third direction being perpendicular to the first direction.
5. 5. The method of manufacturing a semiconductor memory device according to claim 1, wherein the material of the word line cap includes at least one of silicon nitride, polysilicon, silicon germanium, and silicon oxide.
6. 6. The method of manufacturing a semiconductor memory device according to claim 1, wherein the step of depositing a conductive material in the plurality of first grooves to form a word line structure comprises: depositing a first conductive material in the plurality of first grooves to form an initial word line structure; Forming a first sub-recess on the initial word line structure, and depositing a second conductive material in the first sub-recess to form a word line structure; the first conductive material includes at least one of titanium and titanium nitride; The second conductive material comprises tungsten.
7. 7. The method of manufacturing a semiconductor memory device according to claim 1, wherein before the step of forming a plurality of first grooves in the first direction on the substrate, the method further comprises: A buried layer is deposited on the substrate.
8. 8. The method of manufacturing a semiconductor memory device according to claim 7, wherein the step of forming a plurality of first grooves on the substrate in the first direction comprises: Forming an etching window on the buried layer along the first direction; And forming a plurality of first grooves on the substrate along a first direction according to the etching window.
9. 9. The method for manufacturing a semiconductor memory device according to claim 1, wherein the method further comprises: Forming a bit line node contact over one active region between two word line structures passing through the active region; a bit line structure is formed over the bit line node contact along a fourth direction, the fourth direction being perpendicular to the first direction.
10. 10. The method for manufacturing a semiconductor memory device according to claim 9, wherein the method further comprises: Forming a storage node contact portion above the active region, wherein the bottom of the storage node contact portion is electrically connected with a source drain region formed at the top of the active region; Forming a landing pad over the storage node contact, the landing pad being electrically connected to the storage node contact; A data storage member is formed over the landing pad.

Description

Method for manufacturing semiconductor memory device Technical Field The invention relates to the technical field of semiconductor processing, in particular to a preparation method of a semiconductor memory device. Background With the rapid development of science and technology, the volume of semiconductor memory devices is beginning to become smaller and smaller. However, as the size of semiconductor memory devices becomes smaller, the difficulty in processing the semiconductor memory devices becomes greater. Particularly for the fabrication of semiconductor memory devices having buried channel transistors (BCAT, buried CHANNEL ARRAY transistors), the fabrication difficulty is particularly great. In the conventional process of manufacturing a semiconductor memory device having buried channel transistors, it is common to form active regions on a substrate, then form buried channel transistors intersecting a plurality of active regions on the substrate, and then form bit lines, bit line node contacts, storage node contacts, and the like. However, the method is easy to etch the active region before forming the buried channel transistor, if the active region is collapsed, and the buried channel transistor spans a plurality of regions of different materials, so that the buried channel transistor is easy to collapse in the process of forming the buried channel transistor, and the manufacturing yield of the semiconductor memory device is seriously reduced. Disclosure of Invention In order to solve the problems, the method for manufacturing the semiconductor memory device provided by the invention can avoid collapse of the active region and the word line structure in the forming process or the etching process by forming the word line structure on the top of the substrate and then forming the active region crossing the word line structure on the substrate, thereby improving the manufacturing yield of the semiconductor memory device. The invention provides a method for preparing a semiconductor memory device, which comprises the following steps: Providing a substrate; Forming a plurality of first grooves along a first direction on the substrate; depositing conductive material in the plurality of first grooves to form a word line structure; forming word line covers in the first grooves; forming a plurality of second grooves on the substrate along a second direction, wherein the first direction intersects with the second direction; An active region is formed within the second recess. Optionally, before the step of depositing the conductive material in the plurality of first grooves, the method further comprises: And forming a gate dielectric layer on the side walls and the bottom surfaces of the plurality of first grooves. Optionally, the gate dielectric layer material includes a silicon oxide layer, a thermal oxide layer, or a high-k dielectric layer. Optionally, the width of the word line cover in a third direction is not smaller than the width of the word line structure in the third direction, and the third direction is perpendicular to the first direction. Optionally, the material of the word line cap includes at least one of silicon nitride, polysilicon, silicon germanium, and silicon oxide. Optionally, the step of depositing a conductive material in the plurality of first grooves to form a word line structure includes: depositing a first conductive material in the plurality of first grooves to form an initial word line structure; Forming a first sub-recess on the initial word line structure, and depositing a second conductive material in the first sub-recess to form a word line structure; the first conductive material includes at least one of titanium and titanium nitride; The second conductive material comprises tungsten. Optionally, before the step of forming a plurality of first grooves on the substrate along the first direction, the method further comprises: A buried layer is deposited on the substrate. Optionally, the step of forming a plurality of first grooves on the substrate along a first direction includes: Forming an etching window on the buried layer along the first direction; And forming a plurality of first grooves on the substrate along a first direction according to the etching window. Optionally, the method further comprises: Forming a bit line node contact over one active region between two word line structures passing through the active region; a bit line structure is formed over the bit line node contact along a fourth direction, the fourth direction being perpendicular to the first direction. Optionally, the method further comprises: Forming a storage node contact portion above the active region, wherein the bottom of the storage node contact portion is electrically connected with a source drain region formed at the top of the active region; Forming a landing pad over the storage node contact, the landing pad being electrically connected to the storage node contact; A data storage member is