CN-115332314-B - Semiconductor device with a semiconductor layer having a plurality of semiconductor layers

Abstract

The semiconductor device includes a substrate, a first gallium nitride type high electron mobility transistor, a second gallium nitride type high electron mobility transistor, a first inner connector, a second inner connector. The substrate includes a first type doped semiconductor region and a second type doped semiconductor region. The first gallium nitride type high electron mobility transistor covers the first region on the first type doped semiconductor region and the second type doped semiconductor region. The second gallium nitride type high electron mobility transistor covers the first type doped semiconductor region and a second region on the second type doped semiconductor region. The first region and the second region are spaced apart from each other. The first inner connector is connected with the first area, and the width of the first inner connector is larger than the source-drain distance of the first gallium nitride type high electron mobility transistor. The second inner connector is connected with the second area, and the width of the second inner connector is larger than the source-drain distance of the second gallium nitride type high electron mobility transistor.

Inventors

• DU WEIXING
• You Zhengsheng

Assignees

• 英诺赛科(苏州)科技有限公司

Dates

Publication Date

20260508

Application Date

20201020

Claims (18)

1. 1. A semiconductor device, comprising: a substrate including a plurality of first type doped semiconductor regions and a plurality of second type doped semiconductor regions, the plurality of first type doped semiconductor regions and the plurality of second type doped semiconductor regions extending along a first direction and being alternately arranged along a second direction, the first direction and the second direction being different; A first gallium nitride type high electron mobility transistor disposed above the substrate and covering the plurality of first type doped semiconductor regions and the first regions on the plurality of second type doped semiconductor regions; A second gallium nitride type high electron mobility transistor disposed over the substrate and covering the plurality of first type doped semiconductor regions and a second region on the plurality of second type doped semiconductor regions, wherein the first region and the second region are spaced apart from each other; a first inner connector disposed above the substrate and connecting the first regions on the first and second doped semiconductor regions, the first inner connector having a width larger than a source-drain pitch of the first GaN-type HEMT, and A second inner connector disposed over the substrate and connecting the plurality of first-type doped semiconductor regions and the second regions on the plurality of second-type doped semiconductor regions, the second inner connector having a width greater than a source-drain pitch of the second gallium nitride-type high electron mobility transistor; the first and second inner connectors are electrically connected with external power sources of different voltages through connection pads.
2. 2. The semiconductor device of claim 1, wherein the first region and the second region are separated by at least more than one of the plurality of first-type doped semiconductor regions or the plurality of second-type doped semiconductor regions.
3. 3. The semiconductor device of claim 1, wherein the first inner connector covers and spans a plurality of the plurality of first-type doped semiconductor regions and the plurality of second-type doped semiconductor regions.
4. 4. The semiconductor device of claim 1, wherein the second inner connector covers and spans a plurality of the plurality of first-type doped semiconductor regions and the plurality of second-type doped semiconductor regions.
5. 5. The semiconductor device of claim 1, wherein a distance between the first and second inner connectors is shorter than a distance between the first and second gallium nitride-type high electron mobility transistors.
6. 6. The semiconductor device of claim 1, wherein a plurality of adjacent doped semiconductor regions of the first type and doped semiconductor regions of the second type form a PNP structure.
7. 7. The semiconductor device of claim 1, wherein the number of first-type doped semiconductor regions and second-type doped semiconductor regions traversed or spanned by the first inner connector is greater than the number of first-type doped semiconductor regions and second-type doped semiconductor regions traversed or spanned by the first gallium nitride-type high electron mobility transistor.
8. 8. The semiconductor device of claim 1, wherein the number of first-type doped semiconductor regions and second-type doped semiconductor regions traversed or spanned by the second inner connector is greater than the number of first-type doped semiconductor regions and second-type doped semiconductor regions traversed or spanned by the second gallium nitride-type high electron mobility transistor.
9. 9. The semiconductor device of claim 1, wherein the first and second inner connectors are on a same side of the first and second gallium nitride-type high electron mobility transistors.
10. 10. A semiconductor device, comprising: a substrate including a plurality of first type doped semiconductor regions and a plurality of second type doped semiconductor regions, the plurality of first type doped semiconductor regions and the plurality of second type doped semiconductor regions extending along a first direction and being alternately arranged along a second direction, the first direction and the second direction being different; A first gallium nitride type high electron mobility transistor disposed above the substrate and covering the plurality of first type doped semiconductor regions and the first regions on the plurality of second type doped semiconductor regions; A second gallium nitride type high electron mobility transistor disposed above the substrate and covering second regions on the plurality of first type doped semiconductor regions and the plurality of second type doped semiconductor regions, wherein the first regions and the second regions are arranged along the second direction; A first inner connector disposed over the substrate and connecting the plurality of first-type doped semiconductor regions and the first regions on the plurality of second-type doped semiconductor regions, the first inner connector and the first gallium nitride-type high electron mobility transistor being arranged along the first direction; and A second inner connector disposed over the substrate and connecting the plurality of first-type doped semiconductor regions and the second regions on the plurality of second-type doped semiconductor regions, the second inner connector and the second gallium nitride-type high electron mobility transistor being arranged along the first direction; the first and second inner connectors are electrically connected with external power sources of different voltages through connection pads.
11. 11. The semiconductor device of claim 10, wherein the first region and the second region are separated by at least more than one of the plurality of first-type doped semiconductor regions or the plurality of second-type doped semiconductor regions.
12. 12. The semiconductor device of claim 10, wherein the first inner connector covers and spans a plurality of first-type doped semiconductor regions and the plurality of second-type doped semiconductor regions along the second direction.
13. 13. The semiconductor device of claim 10, wherein the second inner connector covers and spans a plurality of first-type doped semiconductor regions and the plurality of second-type doped semiconductor regions along the second direction.
14. 14. The semiconductor device of claim 10, wherein a distance between the first and second inner connectors is shorter than a distance between the first and second gallium nitride-type high electron mobility transistors.
15. 15. The semiconductor device of claim 10, wherein a plurality of adjacent doped semiconductor regions of the first type and doped semiconductor regions of the second type form a PNP structure.
16. 16. The semiconductor device of claim 10, wherein the number of first-type doped semiconductor regions and second-type doped semiconductor regions traversed or spanned by the first inner connector is greater than the number of first-type doped semiconductor regions and second-type doped semiconductor regions traversed or spanned by the first gallium nitride-type high electron mobility transistor.
17. 17. The semiconductor device of claim 10, wherein the number of first-type doped semiconductor regions and second-type doped semiconductor regions traversed or spanned by the second inner connector is greater than the number of first-type doped semiconductor regions and second-type doped semiconductor regions traversed or spanned by the second gallium nitride-type high electron mobility transistor.
18. 18. The semiconductor device of claim 10, wherein the first and second inner connectors are on a same side of the first and second gallium nitride-type high electron mobility transistors.

Description

Semiconductor device with a semiconductor layer having a plurality of semiconductor layers The present application is a divisional application of chinese patent application 202080003405.4 entitled "semiconductor device and method of manufacturing a semiconductor device" filed 10/20/2020. Technical Field The present invention relates generally to semiconductor devices. More particularly, the present invention relates to semiconductor devices having high electron mobility transistors doped into a substrate to achieve good voltage distribution. Background In recent years, in semiconductor devices, deep research into high electron mobility transistors (high electron mobility transistor; HEMTs) has begun to prevail, such as high power switches and high frequency application devices. HEMTs utilize a heterojunction (heterojunction) between two materials with different energy bandgaps to form a quantum well (quantum well) like structure that accommodates a two-dimensional electron gas (two-dimensional electron gas;2 DEG) region to meet the requirements of high power/high frequency devices. Examples of devices having a heterojunction structure include, in addition to high electron mobility transistors, heterojunction bipolar transistors (heterojunction bipolar transistor; HBTs), heterojunction field effect transistors (heterojunction FIELD EFFECT transistors; HFETs), and modulation-doped field effect transistors (MODFETs). Currently, high electron mobility transistors are in need of improving the productivity to meet the conditions of mass production. Disclosure of Invention One aspect of the present disclosure provides a semiconductor device including a substrate, a first gallium nitride type high electron mobility transistor, a second gallium nitride type high electron mobility transistor, a first inner connector, and a second inner connector. The substrate comprises a plurality of first type doped semiconductor regions and a plurality of second type doped semiconductor regions, wherein the plurality of first type doped semiconductor regions and the plurality of second type doped semiconductor regions extend along a first direction and are alternately arranged along a second direction, and the first direction and the second direction are different. The first gallium nitride type high electron mobility transistor is disposed above the substrate and covers the plurality of first type doped semiconductor regions and the first regions on the plurality of second type doped semiconductor regions. A second gallium nitride type high electron mobility transistor is disposed over the substrate and covers the plurality of first type doped semiconductor regions and a second region on the plurality of second type doped semiconductor regions, wherein the first region and the second region are spaced apart from each other. A first inner connector is disposed over the substrate and connects the plurality of first-type doped semiconductor regions and the first regions on the plurality of second-type doped semiconductor regions, and a width of the first inner connector is greater than a source-drain spacing of the first GaN high electron mobility transistor. A second inner connector is disposed over the substrate and connects the plurality of first-type doped semiconductor regions and the second regions on the plurality of second-type doped semiconductor regions, and a width of the second inner connector is greater than a source-drain spacing of the second GaN high electron mobility transistor. According to another aspect of the present disclosure, there is provided a semiconductor device including a substrate, a first gallium nitride-type high electron mobility transistor, a second gallium nitride-type high electron mobility transistor, a first inner connector, and a second inner connector. The substrate comprises a plurality of first type doped semiconductor regions and a plurality of second type doped semiconductor regions, wherein the plurality of first type doped semiconductor regions and the plurality of second type doped semiconductor regions extend along a first direction and are alternately arranged along a second direction, and the first direction and the second direction are different. The first gallium nitride type high electron mobility transistor is disposed above the substrate and covers the plurality of first type doped semiconductor regions and the first regions on the plurality of second type doped semiconductor regions. The second gallium nitride type high electron mobility transistor is configured above the substrate and covers the plurality of first type doped semiconductor regions and the second regions on the plurality of second type doped semiconductor regions, wherein the first regions and the second regions are arranged along the second direction. A first inner connector is disposed over the substrate and connects the first regions on the plurality of first-type doped semiconductor regions and the pluralit